Fpga Mezzanine Card Interface; Fmc Hpc0 Connector J5 - Xilinx ZCU106 User Manual

Table 3-42: PS-GTR Bank 505 Interface Connections (Cont'd)
XCZU7EV
XCZU7EV Pin Name
(U1) Pin
N29 PS_MGTRTXP3
N30 PS_MGTRTXN3
N33 PS_MGTRRXP3
N34 PS_MGTRRXN3
T27 PS_MGTREFCLK0P
T28 PS_MGTREFCLK0N
P27 PS_MGTREFCLK1P
P28 PS_MGTREFCLK1N
M27 PS_MGTREFCLK2P
M28 PS_MGTREFCLK2N
M31 PS_MGTREFCLK3P
M32 PS_MGTREFCLK3N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.

FPGA Mezzanine Card Interface

[Figure 2-1, callouts 32, 33]
The ZCU106 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC)
specification [Ref 23]
J5 (HPC0) and J4 (HPC1). HPC connectors use a 10 x 40 form factor, populated with 400
pins. The connectors are keyed so that a mezzanine card, when installed in either of these
FMC connectors on the ZCU106 evaluation board, faces away from the board.

FMC HPC0 Connector J5

[Figure 2-1, callout 32]
The FMC connector at J5 (HPC0) implements a subset of the full FMC HPC connectivity:
• 68 single-ended, or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• Eight GTH transceiver DP differential pairs
• Two GBTCLK differential clocks
• 159 ground and 15 power connections
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
(2)
Schematic Net Name
(1)
GT3_SATA1_TX_P
(1)
GT3_SATA1_TX_N
(1)
GT3_SATA1_RX_P
(1)
GT3_SATA1_RX_N
NC
NC
(1)
GTR_REF_CLK_SATA_C_P
(1)
GTR_REF_CLK_SATA_C_N
(1)
GTR_REF_CLK_USB3_C_P
(1)
GTR_REF_CLK_USB3_C_N
(1)
GTR_REF_CLK_DP_C_P
(1)
GTR_REF_CLK_DP_C_N
by providing subset implementations of high pin count connectors at
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected To
Pin No. Pin Name
2 HTX_P
3 HTX_N
6 HRX_P
5 HRX_N
NA NA
NA NA
35 OUT3_P
34 OUT3_N
31 OUT2_P
30 OUT2_N
24 OUT0_P
23 OUT0_N
Device
SATA P9
NA
SI5341B U69
104
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