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Zynq UltraScale+ RFSoC
ZCU208 and ZCU216 RF
Data Converter Evaluation
Tool
User Guide
UG1433 (v1.2) October 27, 2021
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Table of Contents
Related Manuals for Xilinx Zynq UltraScale+ RFSoC ZCU208
Summary of Contents for Xilinx Zynq UltraScale+ RFSoC ZCU208
- Page 1 Tool User Guide UG1433 (v1.2) October 27, 2021 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non- inclusive language from our products and related collateral. We’ve launched an internal initiative to remove language that could exclude people or reinforce historical biases, including terms embedded in our software and IPs.
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Page 2: Revision History
Removed SetSignalDetector and GetSignalDetector commands. Revised description for RfclkWriteReg. Added Appendix B: Command List GetExtParentClkList, GetExtParentClkConfig, SetMMCMFin, GetMMCMFin, and GetMTS_Setup commands. 03/23/2020 Version 1.0 Initial release. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 3: Table Of Contents
CLK104 on TCA9548 Multiplexer ............... 26 Appendix B: Command List ..................27 Appendix C: Additional Resources and Legal Notices ......34 Xilinx Resources.........................34 Documentation Navigator and Design Hubs.................34 UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... - Page 4 References..........................34 Please Read: Important Legal Notices................... 35 UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
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Page 5: Chapter 1: Introduction
Gen 3 RF data converters. Advantages of using this tool include acceleration of the product design cycle, reduction of product go-to-market expense, and quicker revenue realization. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 6: Chapter 2: Overview
Chapter 3: Hardware Design) • FPGA embedded software design (see Chapter 4: Software Design and Build) • GUI (see RF Data Converter Interface User Guide (UG1309)) UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 7: Installation
RF DC Evaluation Tool for ZCU208 Board Quick Start or the RF DC Evaluation Tool for ZCU216 Board Quick Start website for installation and folder structure information. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 8: Chapter 3: Hardware Design
• Time division duplex (TDD) power up/down block to control the TDD real-time signal (RTS) pins of ADCs and DACs The following figure shows the high-level hardware architecture. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 9: Block Ram Generation And Capture
The block RAM generation and capture are described in the "RF Analyzer" section in the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269). UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 10: Rf-Dac Ddr
RF-ADC waveform is fed into the DMA and captured into the DDR memory. To allow the software to control the DMA accurately, a TLAST UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... - Page 11 S01_AXI S07_ARB_REQ_SUPPRESS c0_ddr4_ul_clk_sync_rst S08_ARB_REQ_SUPPRESS DDR4 SDRAM (MIG) AXI SmartConect (Pre-Production) S09_ARB_REQ_SUPPRESS (Pre-Production) S10_ARB_REQ_SUPPRESS S11_ARB_REQ_SUPPRESS S12_ARB_REQ_SUPPRESS S13_ARB_REQ_SUPPRESS S14_ARB_REQ_SUPPRESS S15_ARB_REQ_SUPPRESS AXI4-Stream Interconnect (Pre-Production) s00_axi s_axi_ ps_adc_ddr X23665-012320 UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
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Page 12: Clocking Scheme
For the RF-DAC, only the MMCM is used. The path used in the MTS case is shown in red. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 13: Tdd Control Block
The block can be used as a reference on how to drive the real-time signal TDD pins, power and performance measurements, and debugging. The block has the following features: UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... - Page 14 Counter Counter TDD RTS Pins to ADC/DAC Decoder Guard Length DL/UL Map AXI Registers X25660-081321 Ports The following table lists the TDD control block ports. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 15 Command log window of the RF Evaluation tool GUI (RF Data Converter Interface User Guide (UG1309). The following examples show the command sequences for DAC and ADC, respectively. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 16 4. To set up an ADC trigger on a specific frame and symbol: • Write symbol and frame trigger registers. SetTDDRTSTrigSlot 5 5. ○ SetTDDRTSTrigSlot symbol frame. ○ UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 17 This controls the hw_trigger_en pins. In this example, it enables the trigger on tile 1. ○ • Write 1 in the trigger register. SetTDDRTSTrig 1. ○ This controls the hw_trigger pins. ○ UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
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Page 18: Chapter 4: Software Design And Build
The control path and datapath are implemented using two different TCP sockets. The components in the software flows are implemented in the user space and the kernel space. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 19: User Space Components
The Linux user space components used are: • The rftool is the Linux application that receives commands over the Ethernet from the PC GUI and performs appropriate actions. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 20: Kernel Space Components
RFDC user space driver libmetal to configure RFDC hardware. • MMCM control is reconfiguring the MMCM/PLL depending on tile clock requirement. The following figure shows the application execution flow. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 21: Software Build
-t project -s <bsp> -n <project_name> 3. To build the project, enter: cd <project_name> petalinux-build -v 4. To make the images for the SD card, enter: UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... - Page 22 --fpga ./images/linux/system.bit --pmufw ./pre- built/linux/images/pmufw.elf --u-boot ./images/linux/u-boot.elf 5. Copy these files to the SD card: <project_name>/images/linux/BOOT.BIN <project_name>/images/linux/image.ub <project_name>/images/linux/boot.scr autostart.sh (copy from the Externals\image\216 folder) UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
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Page 23: Chapter 5: Protocol Specifications
(see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269)). The command can be split into these categories. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 24: Protocol Rules
• Any log or messages from metal-log can be returned via the getlog command; the \r\n characters are replaced from any log messages with "|" and a single \n appended at the end UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 25: Socket Interface
TCP port 8082. The TCP socket uses a Linux TCP/IP stack, which uses the GEM Ethernet controller and driver for sending packets. Because the TCP socket is used, it is possible to run the GUI on any networked machines. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 26: Appendix A: Software Design Notes - Multimaster Access Of Clk104 On Tca9548 Multiplexer
RFSoC. The operation to select the CLK104 device on the multiplexer and read/write operation is completed in three steps in the I2C driver. When one master is accessing the device, the other master should not access it. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... -
Page 27: Appendix B: Command List
Type, Tile, Block Cf. PG269 BlockStatus.DataPathClocksStatus, BlockStatus.IsFIFOFlagsAsserted, BlockStatus.IsFIFOFlagsEnabled Tile, Block, CalFreezePtr.CalFrozen, CalFreezePtr.FreezeCalibration, GetCalFreeze Tile, Block Cf. PG269 CalFreezePtr.DisableFreezePin GetCalibrationMode Tile, Block Tile, Block, CalibrationMode Cf. PG269 UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide... - Page 28 Cf. PG269 Type, Tile, Block, Mixer_Settings.Freq, Mixer_Settings.PhaseOffset, Mixer_Settings.EventSource, Mixer_Settings.MixerType, GetMixerSettings Type, Tile, Block Cf. PG269 Mixer_Settings.CoarseMixFreq, Mixer_Settings.MixerMode, Mixer_Settings.FineMixerScale GetMTSEnable Type, Tile Type, Tile, Enable Cf. PG269 UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 29 None Cf. PG269 RF_WriteReg32 Offset, Value None Cf. PG269 Tile, Block, SetCalFreeze CalFreezePtr.FreezeCalibration, None Cf. PG269 CalFreezePtr.DisableFreezePin SetCalibrationMode Tile, Block, Calibration Mode None Cf. PG269 UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 30 Cf. PG269 clkout0_div, clkout0_frac SetNyquistZone Type, Tile, Block, NyquistZone None Cf. PG269 Type, Tile, Block, QMC_Settings.EnablePhase, QMC_Settings.EnableGain, SetQMCSettings QMC_Settings.GainCorrectionFactor, None Cf. PG269 QMC_Settings.PhaseCorrectionFactor, QMC_Settings.OffsetCorrectionFactor, QMC_Settings.EventSource UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 31 TCS file) Configure LMK clock SetExtParentclk Board_id, freq Board_id, freq with requested frequency. Configure PLL (LMX) SetExtPllClkRate Board_id, Pll_src, freq Board_id, Pll_Src, freq with requested frequency. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 32 Type, TDD_ModePin None control, LSB channel 0, MSB channel 15. Get the channel to GetTDDRTSPinCtrl Type Type, TDD_ModePin control, LSB channel 0, MSB channel 15. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
- Page 33 Enables None hw_trigger_en on capture mem, per tile. Reset the counters in SetTDDRTSRst Reset None the TDD block. Read the reset SetTDDRTSRst None Reset register. UG1433 (v1.2) October 27, 2021 www.xilinx.com Send Feedback RF Data Converter Evaluation Tool User Guide...
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Page 34: Appendix C: Additional Resources And Legal Notices
• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •... - Page 35 IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...