Psmio - Xilinx ZCU106 User Manual

Table 3-4: DDR4 Component Memory Connection to the XCZU7EV MPSoC (Cont'd)
XCZU7EV
Net Name
(U1) Pin
AF10 DDR4_ODT
AD12 DDR4_CS_B
The ZCU106 board DDR4 64-bit component memory interface adheres to the constraints
guidelines documented in the "PCB Guidelines for DDR4" section of UltraScale Architecture
PCB Design User Guide
impedance implementations. Other memory interface details are also available in the
UltraScale Architecture FPGAs Memory Interface Solutions Product Guide (PG150)
more details, see the Micron MT40A256M16GE-075E data sheet at the Micron website
[Ref 15].

PSMIO

Table 3-5 provides PS MIO peripheral mapping implemented on the ZCU106 board. See the
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
on PS MIO peripheral mapping.
Table 3-5: MIO Peripheral Mapping
MIO[0:25] Bank 500
0 QSPI
1 QSPI
2 QSPI
3 QSPI
4 QSPI
5 QSPI
6 Not assigned/no connect
7 QSPI
8 QSPI
9 QSPI
10 QSPI
11 QSPI
12 QSPI
13 GPIO
14 I2C0
15 I2C0
16 I2C1
17 I2C1
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
I/O Standard
SSTL12_DCI
SSTL12_DCI
(UG583)[Ref 3]. The ZCU106 DDR4 component interface is a 40Ω
MIO[26:51] Bank 501
26 PMU IN
27 DPAUX
28 DPAUX
29 DPAUX
30 DPAUX
31 Not assigned/no connect
32 PMU OUT
33 PMU OUT
34 PMU OUT
35 PMU OUT
36 PMU OUT
37 PMU OUT
38 GPIO
39 SD1
40 SD1
41 SD1
42 SD1
43
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Chapter 3: Board Component Descriptions
DDR4 Component Memory
Pin # Pin Name
K3 ODT
L7 CS_B
[Ref 2]
MIO[52:77] Bank 502
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Ref. Des.
U2,U99-U101
U2,U99-U101
[Ref 4]. For
for more information
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
USB0
GEM3
GEM3
GEM3
GEM3
GEM3
GEM3
37
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