User Pmod Gpio Headers - Xilinx ZCU106 User Manual

User PMOD GPIO Headers

[Figure 2-1, callout 20, 21]
The ZCU106 evaluation board supports two PMOD GPIO headers J55 (right-angle female)
and J87 (vertical male). The 3.3V PMOD nets are level-shifted and wired to the XCZU7EV
device U1 banks 28, 66, and 68.
Table 3-33 lists the connections between the XCZU7EV MPSoC and the PMOD connectors.
Maximum PMOD interface speed is 110 Mb/s.
X-Ref Target - Figure 3-31
Table 3-33: XCZU7EV U1 to PMOD Connections
XCZU7EV (U1) Pin
B23
A23
F25
E20
K24
L23
L22
D7
AN8
AN9
AP11
AN11
AP9
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
Figure 3-31 shows the GPIO PMOD headers J55 and J87.
Figure 3-31: PMOD Connectors
Net Name
PMOD0_0
PMOD0_1
PMOD0_2
PMOD0_3
PMOD0_4
PMOD0_5
PMOD0_6
PMOD0_7
PMOD1_0
PMOD1_1
PMOD1_2
PMOD1_3
PMOD1_4
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Chapter 3: Board Component Descriptions
I/O Standard
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
Send Feedback
X19195-050117
PMOD Pin
J55.1
J55.3
J55.5
J55.7
J55.2
J55.4
J55.6
J55.8
J87.1
J87.3
J87.5
J87.7
J87.2
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