Xilinx ZCU106 User Manual page 140

set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H21
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C23
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN D22
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN H26
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN J25
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F20
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN G20
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E22
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN F22
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN A21
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN A20
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN D19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN E19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C22
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C21
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN D21
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN D20
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN A19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN A18
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C19
set_propertyIOSTANDARD
set_propertyPACKAGE_PIN C18
set_propertyIOSTANDARD
#HDMI
set_property PACKAGE_PIN AP3
set_property PACKAGE_PIN AP4
set_property PACKAGE_PIN AN1
set_property PACKAGE_PIN AN2
set_property PACKAGE_PIN AL1
set_property PACKAGE_PIN AL2
set_property PACKAGE_PIN AN5
set_property PACKAGE_PIN AN6
set_property PACKAGE_PIN AM3
set_property PACKAGE_PIN AM4
set_property PACKAGE_PIN AL5
set_property PACKAGE_PIN AL6
set_property PACKAGE_PIN AD7
set_property PACKAGE_PIN AD8
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
LVDS [get_ports "FMC_HPC1_LA06_N"] ;
[get_ports "FMC_HPC1_LA06_P"] ;
LVDS [get_ports "FMC_HPC1_LA06_P"] ;
[get_ports "FMC_HPC1_LA07_N"] ;
LVDS [get_ports "FMC_HPC1_LA07_N"] ;
[get_ports "FMC_HPC1_LA07_P"] ;
LVDS [get_ports "FMC_HPC1_LA07_P"] ;
[get_ports "FMC_HPC1_LA08_N"] ;
LVDS [get_ports "FMC_HPC1_LA08_N"] ;
[get_ports "FMC_HPC1_LA08_P"] ;
LVDS [get_ports "FMC_HPC1_LA08_P"] ;
[get_ports "FMC_HPC1_LA09_N"] ;
LVDS [get_ports "FMC_HPC1_LA09_N"] ;
[get_ports "FMC_HPC1_LA09_P"] ;
LVDS [get_ports "FMC_HPC1_LA09_P"] ;
[get_ports "FMC_HPC1_LA10_N"] ;
LVDS [get_ports "FMC_HPC1_LA10_N"] ;
[get_ports "FMC_HPC1_LA10_P"] ;
LVDS [get_ports "FMC_HPC1_LA10_P"] ;
[get_ports "FMC_HPC1_LA11_N"] ;
LVDS [get_ports "FMC_HPC1_LA11_N"] ;
[get_ports "FMC_HPC1_LA11_P"] ;
LVDS [get_ports "FMC_HPC1_LA11_P"] ;
[get_ports "FMC_HPC1_LA12_N"] ;
LVDS [get_ports "FMC_HPC1_LA12_N"] ;
[get_ports "FMC_HPC1_LA12_P"] ;
LVDS [get_ports "FMC_HPC1_LA12_P"] ;
[get_ports "FMC_HPC1_LA13_N"] ;
LVDS [get_ports "FMC_HPC1_LA13_N"] ;
[get_ports "FMC_HPC1_LA13_P"] ;
LVDS [get_ports "FMC_HPC1_LA13_P"] ;
[get_ports "FMC_HPC1_LA14_N"] ;
LVDS [get_ports "FMC_HPC1_LA14_N"] ;
[get_ports "FMC_HPC1_LA14_P"] ;
LVDS [get_ports "FMC_HPC1_LA14_P"] ;
[get_ports "FMC_HPC1_LA15_N"] ;
LVDS [get_ports "FMC_HPC1_LA15_N"] ;
[get_ports "FMC_HPC1_LA15_P"] ;
LVDS [get_ports "FMC_HPC1_LA15_P"] ;
[get_ports "FMC_HPC1_LA16_N"] ;
LVDS [get_ports "FMC_HPC1_LA16_N"] ;
[get_ports "FMC_HPC1_LA16_P"] ;
LVDS [get_ports "FMC_HPC1_LA16_P"] ;
[get_ports "HDMI_RX0_C_N"] ;
[get_ports "HDMI_RX0_C_P"] ;
[get_ports "HDMI_RX1_C_N"] ;
[get_ports "HDMI_RX1_C_P"] ;
[get_ports "HDMI_RX2_C_N"] ;
[get_ports "HDMI_RX2_C_P"] ;
[get_ports "HDMI_TX0_N"] ;
[get_ports "HDMI_TX0_P"] ;
[get_ports "HDMI_TX1_N"] ;
[get_ports "HDMI_TX1_P"] ;
[get_ports "HDMI_TX2_N"] ;
[get_ports "HDMI_TX2_P"] ;
[get_ports "HDMI_SI5324_OUT_C_N"] ;
[get_ports "HDMI_SI5324_OUT_C_P"] ;
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Appendix B: Master Constraints File Listing
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