Xilinx ZCU106 User Manual page 145

set_property IOSTANDARD
#SFP1
set_property PACKAGE_PIN AF20
set_property IOSTANDARD
set_property PACKAGE_PIN W1
set_property PACKAGE_PIN W2
set_property PACKAGE_PIN W5
set_property PACKAGE_PIN W6
set_property PACKAGE_PIN AF20
set_property IOSTANDARD
#SFP COMMON
set_property PACKAGE_PIN W9
set_property PACKAGE_PIN W10
#SPF CLOCK RECOVERY
set_property PACKAGE_PIN G11
set_property IOSTANDARD
set_property PACKAGE_PIN H11
set_property IOSTANDARD
#I2C BUS
#I2C0
set_property PACKAGE_PIN AE19
set_property IOSTANDARD
set_property PACKAGE_PIN AH23
set_property IOSTANDARD
#I2C1
set_property PACKAGE_PIN AL21
set_property IOSTANDARD
set_property PACKAGE_PIN AH19
set_property IOSTANDARD
#SYSMON I2C
set_property PACKAGE_PIN B20
set_property IOSTANDARD
set_property PACKAGE_PIN A22
set_property IOSTANDARD
#MIO DISPLAY PORT
#Other net PACKAGE_PIN A30 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27
#Other net PACKAGE_PIN A31 - MIO28_DP_HPD
#Other net PACKAGE_PIN A32 - MIO29_DP_OE
#Other net PACKAGE_PIN A33 - MIO30_DP_AUX_IN
#USER MGT I/O
set_property PACKAGE_PIN AB3
set_property PACKAGE_PIN AB4
set_property PACKAGE_PIN AA5
set_property PACKAGE_PIN AA6
#USER MGT CLOCK
set_property PACKAGE_PIN AA9
set_property PACKAGE_PIN AA10
set_property PACKAGE_PIN U9
set_property PACKAGE_PIN U10
set_property PACKAGE_PIN R9
set_property PACKAGE_PIN R10
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
LVCMOS12 [get_ports "SFP0_TX_DISABLE"] ;
[get_ports "SFP1_TX_DISABLE"] ;
LVCMOS12 [get_ports "SFP1_TX_DISABLE"] ;
[get_ports "SFP1_RX_N"] ;
[get_ports "SFP1_RX_P"] ;
[get_ports "SFP1_TX_N"] ;
[get_ports "SFP1_TX_P"] ;
[get_ports "SFP1_TX_DISABLE"] ;
LVCMOS12 [get_ports "SFP1_TX_DISABLE"] ;
[get_ports "SFP_SI5328_OUT_C_N"] ;
[get_ports "SFP_SI5328_OUT_C_P"] ;
[get_ports "SFP_REC_CLOCK_C_N"] ;
LVDS [get_ports "SFP_REC_CLOCK_C_N"] ;
[get_ports "SFP_REC_CLOCK_C_P"] ;
LVDS [get_ports "SFP_REC_CLOCK_C_P"] ;
[get_ports "PL_I2C0_SCL_LS"] ;
LVCMOS12 [get_ports "PL_I2C0_SCL_LS"] ;
[get_ports "PL_I2C0_SDA_LS"] ;
LVCMOS12 [get_ports "PL_I2C0_SDA_LS"] ;
[get_ports "PL_I2C1_SDA_LS"] ;
LVCMOS12 [get_ports "PL_I2C1_SDA_LS"] ;
[get_ports "PL_I2C1_SCL_LS"] ;
LVCMOS12 [get_ports "PL_I2C1_SCL_LS"] ;
[get_ports "SYSMON_SDA_LS"] ;
LVCMOS18 [get_ports "SYSMON_SDA_LS"] ;
[get_ports "SYSMON_SCL_LS"] ;
LVCMOS18 [get_ports "SYSMON_SCL_LS"] ;
[get_ports "SMA_MGT_RX_C_N"] ;
[get_ports "SMA_MGT_RX_C_P"] ;
[get_ports "SMA_MGT_TX_N"] ;
[get_ports "SMA_MGT_TX_P"] ;
[get_ports "USER_SMA_MGT_CLOCK_C_N"] ;
[get_ports "USER_SMA_MGT_CLOCK_C_P"] ;
[get_ports "USER_MGT_SI570_CLOCK1_C_N"] ;
[get_ports "USER_MGT_SI570_CLOCK1_C_P"] ;
[get_ports "USER_MGT_SI570_CLOCK2_C_N"] ;
[get_ports "USER_MGT_SI570_CLOCK2_C_P"] ;
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Appendix B: Master Constraints File Listing
Bank 501 - PS_MIO28
Bank 501 - PS_MIO29
Bank 501 - PS_MIO30
145
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