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Xilinx ZCU1285 User Manual

Xilinx ZCU1285 User Manual

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ZCU1285 Characterization
Board
User Guide
UG1348 (v1.0) July 16, 2019

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Summary of Contents for Xilinx ZCU1285

  • Page 1 ZCU1285 Characterization Board User Guide UG1348 (v1.0) July 16, 2019...

  • Page 2: Revision History

    Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 07/16/2019 Version 1.0 Initial release. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 3: Table Of Contents

    Table of Contents Revision History .......................2 Chapter 1: ZCU1285 Board Features and Operation ........5 Electrostatic Discharge Caution....................5 Zynq UltraScale+ RFSoC Compatibility..................6 ZCU1285 Board Features......................6 Board Component Locations..................... 8 Power Management......................... 10 Analog Power Module......................17 Serial Transceiver Power Modules..................19 Zynq UltraScale+ RFSoC......................21...
  • Page 4 Write Board EEPROM Data....................... 80 Read Board EEPROM Data....................... 81 Appendix F: Additional Resources and Legal Notices ......83 Xilinx Resources.........................83 Documentation Navigator and Design Hubs.................83 References..........................84 Please Read: Important Legal Notices................... 84 UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 5: Chapter 1: Zcu1285 Board Features And Operation

    ZCU1285 Board Features and Operation ® ® This user guide describes the components, features, and operation of the Xilinx Zynq UltraScale+™ RFSoC ZCU1285 characterization kit. The ZCU1285 kit provides the hardware environment for characterizing and evaluating the radio frequency data converter subsystem (RF- ADC/RF-DAC) and high-speed serial transceivers (GTY/PS-GTR) available on the XCZU39DR-2FFVF1760I Zynq UltraScale+ RFSoC.

  • Page 6: Zynq Ultrascale+ Rfsoc Compatibility

    Chapter 1: ZCU1285 Board Features and Operation Zynq UltraScale+ RFSoC Compatibility The ZCU1285 board is provided with the XCZU39DR-2FFVF1760I Zynq UltraScale+ RFSoC. There are no other pin-compatible devices in this package. ZCU1285 Board Features • XCZU39DR-2FFVF1760I Zynq UltraScale+ RFSoC • Samtec Bulls Eye ®...
  • Page 7 • 4x 4 Gb DDR3 SDRAM PS memory • 1 Gb Quad SPI flash PS memory • PMBus connectivity to the board’s digital power supplies Block Diagram The ZCU1285 block diagram is shown in the following figure. Figure 1: Block Diagram GTR Transceiver QUAD 505...

  • Page 8: Board Component Locations

    Chapter 1: ZCU1285 Board Features and Operation Board Component Locations The following figure shows the ZCU1285 board component locations. Each numbered component shown in the figure is keyed to the table in Board Component Descriptions. CAUTION! Do not remove the rubber feet from the board. The feet provide clearance to prevent short circuits on the back side of the board.
  • Page 9 Chapter 1: ZCU1285 Board Features and Operation Board Component Descriptions Table 1: Board Component Descriptions Callout Reference Designator Feature Description Power Switch 12V Mini-Fit connector (12V Input Power) 12V external power supply connector (12V Input Power, Using External Power Sources)

  • Page 10: Power Management

    Interface, Tab) Power Management 12V Input Power The ZCU1285 board receives 12V main power through J28 (callout 2, Figure 2: Board Component Locations) using the 12V AC adapter included with the ZCU1285 characterization kit. J28 is a 6-pin (2 x 3), right angle, Mini-Fit connector.
  • Page 11 Chapter 1: ZCU1285 Board Features and Operation CAUTION! When supplying 12V through J28, use only the power supply provided for use with this board (Xilinx part number 3800033). CAUTION! Do NOT use a 6-pin, PC ATX power supply connector with J28. The pinout of the 6-pin, PC ATX connector is not compatible with J28 and the board will be damaged if an attempt is made to power it from a PC ATX power supply connector.
  • Page 12 Chapter 1: ZCU1285 Board Features and Operation Figure 3: Board Power Supply Block Diagram Maxim 20751 12V PWR MultiPhase Master Maxim VT1697SBFXQ U118 0.85V at 20A max VCCINT Maxim VT1697SBFXQ U137 0.85V at 20A max Maxim VT1697SBFXQ U138 0.85V at 20A max...
  • Page 13 Chapter 1: ZCU1285 Board Features and Operation Onboard Power System Devices The ZCU1285 board uses power regulators and PMBus-compliant pulse width modulation (PWM) digital controllers from Maxim Integrated to supply the RFSoC logic and utility voltages listed in the following table. The board can also be configured to use an external bench power supply for each voltage.
  • Page 14 Chapter 1: ZCU1285 Board Features and Operation Table 2: Onboard Power System Devices (cont'd) Reference Power Rail Net Device Part Number Description Voltage Designator(s) Name INA226 Current shunt and power ADC_AVCCAUX 1.8V monitor with I2C interface INA226 Current shunt and power DAC_AVCC 0.925V...
  • Page 15 Chapter 1: ZCU1285 Board Features and Operation Using External Power Sources Each voltage rail for the RFSoC logic, multi-gigabit transceivers (MGTs), and RF data converters has an associated Euro-Mag spring-clamp terminal block (callout 3, 14, 20, 26, 29, 30, 40, and 46,...
  • Page 16 Voltage and current monitoring and control for the Maxim power system is available through either the ZCU1285 System Controller or via the Maxim PowerTool software GUI. The ZCU1285 System Controller is the simplest and most convenient way to monitor the voltage and current values for the power rails listed in Onboard Power System Devices.

  • Page 17: Analog Power Module

    RFSoC RF data converters. The analog power module connects to J131, J119, and J120. Two analog power modules are provided with the ZCU1285 board for evaluation. One module is made by Intersil with part number ISL8024DEMO2Z and the other is made by MPS with part number EVREF0102A.
  • Page 18 The following table lists the nominal voltage values for the ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVTT, and DAC_AVCCAUX power rails. It also lists the maximum current rating for each rail supplied by the analog power modules included with the ZCU1285 characterization kit.

  • Page 19: Serial Transceiver Power Modules

    Chapter 1: ZCU1285 Board Features and Operation CAUTION! The analog power module MUST be removed when providing external power to the RF data converter rails. Information about the analog power modules included with the ZCU1285 characterization kit is available from the vendor websites Renesas Power Management...
  • Page 20 The following table lists the nominal voltage values for the MGTAVCC, MGTAVTT, MGTVCCAUX, MGTAVCC_GTR, and MGTAVTT_GTR power rails. It also lists the maximum current rating for each rail supplied by serial transceiver modules included with the ZCU1285 board. Table 5: Serial Transceiver Power Modules...

  • Page 21: Zynq Ultrascale+ Rfsoc

    Note: For information about the serial transceiver power modules, contact Maxim technical support and ask about the MAXREFDES87#. Zynq UltraScale+ RFSoC The ZCU1285 board is populated with the XCZU39DR-2FFVF1760I Zynq UltraScale+ RFSoC at U1 (callout 35, Figure 2: Board Component Locations).
  • Page 22 Chapter 1: ZCU1285 Board Features and Operation Figure 8: JTAG Chain Xilinx Xilinx System Controller Zynq XC7Z010-CLG225 UltraScale+ RFSoC 1.8V TMS_0 Bank 34 (1.8V) Bank 503 (VCCO_MIO) TDO_0 VCCO_MIO DUT_TDI VCCO_MIO TDI_0 FMC3_TDO FMC1 FMC2 FMC3 Connector Connector Connector (not populated)
  • Page 23 MODE 1 (J166) MODE 0 (J165) JTAG QSPI24 QSPI32 NAND eMMC_18 USB 0 PJTAG_0 PJTAG_1 SD1-LS Notes: These boot modes are not directly supported by the ZCU1285 board. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 24 Chapter 1: ZCU1285 Board Features and Operation RFSoC Processor Reference Clock A free-running 33.3333333 MHz clock (U12) is the clock source for the RFSoC processor (PS_REF_CLK). 300 MHz LVDS Oscillator A 300 MHz LVDS oscillator U145 (SiTime SIT9107AI-243N25E300.0000) connects to global clock (GC) pins on the RFSoC.
  • Page 25 Chapter 1: ZCU1285 Board Features and Operation Table 9: User LEDs RFSoC (U1) Schematic Net Reference Name Designator Function Direction IOSTANDARD AM25 USER LED Output LVCMOS18 APP_LED1 DS26 AL24 USER LED Output LVCMOS18 APP_LED2 DS22 AK22 USER LED Output LVCMOS18...
  • Page 26 Chapter 1: ZCU1285 Board Features and Operation Figure 9: User I/O Connector J95 User Pushbuttons SW16 and SW17 (callout 43, Figure 2: Board Component Locations) are active-High user pushbuttons that are connected to RFSoC I/O pins as shown in the following table. These pushbuttons can be used for any user-determined purpose.

  • Page 27: Quad Spi Flash Memory

    Chapter 1: ZCU1285 Board Features and Operation Figure 10: PL and PS SYSMON Power Connections VCCAUX Supply Filter 470 nF 100 nF VCCAUX VCCADC (1.8V +/- 3%) GNDADC 100 nF Digital Analog Regulated 10 µF 100 nF 1.25 +/- 0.2%...

  • Page 28: Sd Card

    Figure 2: Board Component Locations) for booting the RFSoC. The ZCU1285 board supports SD 3.0 and has an SD 3.0 compliant voltage level shifter. To enable SD boot, shunts must be installed for SD1-LS boot mode as indicated in the table in Boot Mode Selection Headers.
  • Page 29 Chapter 1: ZCU1285 Board Features and Operation Figure 11: A: Bulls Eye Connector Pad. B: RF-ADC Connector Pinout. C: RF-DAC Connector Pinout VIN_3 VOUT_3 VIN_0 VOUT_0 VIN_2 VOUT_2 VIN_1 VOUT_1 VIN_1 VOUT_1 VIN_2 VOUT_2 VIN_0 VOUT_0 VIN_3 VOUT_3 RF-ADC Connector Pinout...
  • Page 30 Chapter 1: ZCU1285 Board Features and Operation RF-ADC Pins The information for each RF-ADC pin is listed in the following table. Table 12: RF-ADC Pins RFSoC (U1) Net Name Tile Connector Trace Length (mils) ADC_VIN0_224_P J124 3283.024 ADC_VIN0_224_N J124 3280.721...
  • Page 31 Chapter 1: ZCU1285 Board Features and Operation Table 12: RF-ADC Pins (cont'd) RFSoC (U1) Net Name Tile Connector Trace Length (mils) VCM01_226 VCM23_226 ADC_VIN0_227_P J278 3393.677 ADC_VIN0_227_N J278 3391.355 ADC_VIN1_227_P J278 3274.172 ADC_VIN1_227_N J278 3272.253 ADC_VIN2_227_P J278 3399.961 ADC_VIN2_227_N J278 3397.632...

  • Page 32: Serial Transceivers And Reference Clocks

    DAC_CLK_231_N J279 3835.078 Serial Transceivers and Reference Clocks The ZCU1285 board provides access to all GTY and PS-GTR transceiver and reference clock pins of the RFSoC (callout 33 and 34, Figure 2: Board Component Locations). The serial transceivers are grouped into five sets of four TX-RX lanes, referred to as Quads. There are four GTY Quads (Q128 –Q131), and one PS-GTR Quad (bank 505).
  • Page 33 Chapter 1: ZCU1285 Board Features and Operation All GTY and PS-GTR Quads and their associated reference clocks (CLK0 and CLK1) are brought out to a connector pad, which interfaces with Samtec Bulls Eye connectors used with the Samtec RSP-200723-02-BEYE cable assembly. Contact Samtec, Inc.
  • Page 34 Chapter 1: ZCU1285 Board Features and Operation Table 14: GTY Transceiver Pins (cont'd) Trace Length RFSoC (U1) Net Name Quad Connector (mils) 128_TX0_N J117 3148.266 128_TX0_P J117 3147.413 128_TX1_N J117 3228.503 128_TX1_P J117 3229.157 128_TX2_N J117 3053.346 128_TX2_P J117 3057.162...
  • Page 35 Chapter 1: ZCU1285 Board Features and Operation Table 14: GTY Transceiver Pins (cont'd) Trace Length RFSoC (U1) Net Name Quad Connector (mils) 130_TX3_N J280 2877.072 130_TX3_P J280 2877.059 131_RX0_N J281 2585.706 131_RX0_P J281 2585.352 131_RX1_N J281 3037.05 131_RX1_P J281 3034.196...
  • Page 36 Chapter 1: ZCU1285 Board Features and Operation Table 15: GTY Transceiver Reference Clock Inputs (cont'd) RFSoC (U1) Net Name Quad Connector 131_REFCLK0_N J281 131_REFCLK0_P J281 131_REFCLK1_N J281 131_REFCLK1_P J281 PS-GTR Transceiver Pins Information for each PS-GTR transceiver pin is shown in the following table.

  • Page 37: Superclock-2 Module

    Chapter 1: ZCU1285 Board Features and Operation Table 17: PS-GTR Transceiver Reference Clock Inputs (cont'd) RFSoC (U1) Net Name Bank Connector AD35 PS_REFCLK1_N AC36 PS_REFCLK2_P J194 AC37 PS_REFCLK2_N J156 AB34 PS_REFCLK3_P J158 AB35 PS_REFCLK3_N J159 SuperClock-2 Module The SuperClock-2 Module (callout 6,...

  • Page 38: Superclock-Rf2 Module

    Chapter 1: ZCU1285 Board Features and Operation SuperClock-RF2 Module The SuperClock-RF2 Module (callout 42, Figure 2: Board Component Locations) connects to the clock module interface connector (J170) and provides a programmable, ultra low-noise and low- jitter wideband RF clock source intended for use with the RFSoC RF data converters. It provides three phase-aligned LVDS reference clocks, one single-ended LVCMOS reference clock, four differential pair RF clocks for RF-ADCs, and four differential pair RF clocks for RF-DACs.
  • Page 39 Chapter 1: ZCU1285 Board Features and Operation Figure 15: SuperClock-RF2 Module Features X22899-060719 Table 19: SuperClock-RF2 Interface Connections Callouts Reference Designators Feature Description J12, J13, J14, J15, J16, J17, J18, J19 PLL A RF sampling clock SMA pairs J4, J5, J6, J7, J8, J9...
  • Page 40 Chapter 1: ZCU1285 Board Features and Operation PLL B and C PLL B and C have two differential output SMA pairs each that are used as RF sampling clocks for RF-DACs. Each PLL is programmable to any frequency up to 6.4 GHz with a phase noise performance of -130 dBc/Hz at 1 MHz offset from the carrier and individually programmable output power levels up to 6 dBm.

  • Page 41: Balun Board

    Chapter 1: ZCU1285 Board Features and Operation Balun Board The balun board shown in the following figures is included in the ZCU1285 board kit. It has five baluns accessible through SMA connectors. Two baluns are high frequency, two are low frequency, and one is for a clock channel.
  • Page 42 Chapter 1: ZCU1285 Board Features and Operation Figure 17: Balun Board - Bottom Side X22952-061219 Table 21: Balun Board Details Board Label Manufacturer Part Number Frequency Range HF_CH0 Anaren BD3150N50100AHF 4000-6000 MHz HF_CH1 Anaren BD3150N50100AHF 4000-6000 MHz Anaren BD60120N50100AHF 3500-12000 MHz...

  • Page 43: Fpga Mezzanine Card Interface

    Chapter 1: ZCU1285 Board Features and Operation FPGA Mezzanine Card Interface The ZCU1285 board features one high pin count (HPC) FPGA mezzanine card (FMC) connector and one low pin count (LPC) FMC connector as defined by the VITA 57.1 FPGA mezzanine card...
  • Page 44 Chapter 1: ZCU1285 Board Features and Operation Table 22: FMC2 HPC Connections at JA3 (cont'd) RFSoC (U1) Pin Net Name FMC Pin AH20 FMC2_HA02P AH19 FMC2_HA02N AH21 FMC2_HA03P AJ21 FMC2_HA03N AH18 FMC2_HA04P AJ18 FMC2_HA04N AK21 FMC2_HA05P AK20 FMC2_HA05N AJ17 FMC2_HA06P...
  • Page 45 Chapter 1: ZCU1285 Board Features and Operation Table 22: FMC2 HPC Connections at JA3 (cont'd) RFSoC (U1) Pin Net Name FMC Pin BA19 FMC2_HA21N BA18 FMC2_HA22P BB18 FMC2_HA22N BB21 FMC2_HA23P BB20 FMC2_HA23N AT15 FMC2_HB00_CCP AU15 FMC2_HB00_CCN AJ14 FMC2_HB01_CCP AK14 FMC2_HB01_CCN...
  • Page 46 Chapter 1: ZCU1285 Board Features and Operation Table 22: FMC2 HPC Connections at JA3 (cont'd) RFSoC (U1) Pin Net Name FMC Pin AT13 FMC2_HB17_CCP AU13 FMC2_HB17_CCN AY15 FMC2_HB18P AY14 FMC2_HB18N BA15 FMC2_HB19P BA14 FMC2_HB19N BB16 FMC2_HB20P BB15 FMC2_HB20N BA13 FMC2_HB21P...
  • Page 47 Chapter 1: ZCU1285 Board Features and Operation Table 22: FMC2 HPC Connections at JA3 (cont'd) RFSoC (U1) Pin Net Name FMC Pin FMC2_LA14N FMC2_LA15P FMC2_LA15N FMC2_LA16P FMC2_LA16N FMC2_LA17_CCP FMC2_LA17_CCN FMC2_LA18_CCP FMC2_LA18_CCN FMC2_LA19P FMC2_LA19N FMC2_LA20P FMC2_LA20N FMC2_LA21P FMC2_LA21N FMC2_LA22P FMC2_LA22N FMC2_LA23P...
  • Page 48 Chapter 1: ZCU1285 Board Features and Operation Table 22: FMC2 HPC Connections at JA3 (cont'd) RFSoC (U1) Pin Net Name FMC Pin AL20 FMC2_PRSNT_M2C_L Table 23: FMC3 HPC Connections at JA4 RFSoC (U1) Pin Net Name FMC Pin FMC3_CLK0_M2C_P FMC3_CLK0_M2C_N...
  • Page 49 Chapter 1: ZCU1285 Board Features and Operation Table 23: FMC3 HPC Connections at JA4 (cont'd) RFSoC (U1) Pin Net Name FMC Pin FMC3_LA13P FMC3_LA13N FMC3_LA14P FMC3_LA14N FMC3_LA15P FMC3_LA15N FMC3_LA16P FMC3_LA16N FMC3_LA17_CCP FMC3_LA17_CCN FMC3_LA18_CCP FMC3_LA18_CCN FMC3_LA19P FMC3_LA19N FMC3_LA20P FMC3_LA20N FMC3_LA21P FMC3_LA21N...

  • Page 50: System Controller

    FMC3_LA33P FMC3_LA33N FMC3_PRSNT_M2C_L System Controller The ZCU1285 board uses a Xilinx XC7Z010-CLG225 Zynq-7000 SoC System Controller U38 that can be used to: • Select the output frequencies of the SuperClock2 Module • Select the output frequencies of the SuperClock-RF2 Module •...
  • Page 51 Chapter 1: ZCU1285 Board Features and Operation • SuperClock-2 Module • SuperClock-RF2 Module • System Controller EEPROM • FMC1 connector (not populated) • FMC2 connector • FMC3 connector The following table lists the I2C channel assignments. I2C Component Channel RFSoC and serial transceiver regulators and power monitoring bus (PMBus)

  • Page 52: Usb To Quad-Uart Bridge

    Chapter 1: ZCU1285 Board Features and Operation USB to Quad-UART Bridge A USB to Quad-UART bridge (U32, Silicon Laboratories CP2108) is used for simultaneous serial communication between a host terminal (115200-8-N-1) and the RFSoC PL and PS, and the System Controller. The onboard USB Micro-B receptacle USB connector J1 (callout 5,...

  • Page 53: Default Jumper And Switch Positions

    Chapter 1: ZCU1285 Board Features and Operation The Silicon Labs CP2108 also provides as many as four user-defined GPIO signals for status and control information (see the following table). Table 25: CP2108 USB-to-UART Bridge User GPIO RFSoC (U1) Device (U32)
  • Page 54 Chapter 1: ZCU1285 Board Features and Operation Figure 20: Active Heat Sink The fan power connections are listed in the following table. Table 27: Fan Power Connections Fan Wire Header Pin Black J99.1 - FAN_NEG J99.2 - VCC12_SW Blue J99.3 - NC The following figure shows the heat sink fan power connector J99.
  • Page 55 Chapter 1: ZCU1285 Board Features and Operation Figure 21: Heat Sink Fan Power Connector J99 UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 56: Appendix A: Regulatory And Compliance Information

    CE Safety IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment – Safety, Part 1: General requirements UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 57: Compliance Markings

    Xilinx has met its national obligations to the EU WEEE Directive by registering in those countries to which Xilinx is an importer. Xilinx has also elected to join WEEE Compliance Schemes in some countries to help manage customer returns at end-of-life.

  • Page 58: Appendix B: Default Jumper Settings

    Appendix B Default Jumper Settings The following table lists the jumpers that must be installed on the ZCU1285 board for proper operation. These jumpers must be installed except where specifically noted in this user guide. IMPORTANT! Any jumper not listed in the following table should be left open for normal operation.
  • Page 59 Appendix B: Default Jumper Settings Table 28: Default Jumper Settings (cont'd) Reference Jumper/DIP-Switch Name Board Location Comments Designator Position CLK_DIFF_1_N Lower Middle Installed CLK_DIFF_2_P Lower Middle Installed CLK_DIFF_2_N Lower Middle Installed UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 60: Appendix C: Vita 57.1 Fmc Connector Pinouts

    DP2_C2M_N HB06_P_CC HB07_N LA24_P LA25_N HB08_P HB09_N DP8_C2M_P HB06_N_CC LA24_N HB08_N DP8_C2M_N HB11_P LA29_P HB13_P DP3_C2M_P HB10_P HB11_N LA28_P LA29_N HB12_P HB13_N DP3_C2M_N HB10_N LA28_N HB12_N 3P3VAUX DP7_C2M_P UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 61 HB18_P LA33_P HB21_P 3P3V DP6_C2M_P HB17_P_CC HB18_N LA32_P LA33_N HB20_P HB21_N 12P0V DP6_C2M_N HB17_N_CC LA32_N HB20_N 3P3V DP5_C2M_P VIO_B_M2C VADJ VADJ 3P3V DP5_C2M_N VIO_B_M2C VADJ VADJ 3P3V RES0 UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 62: Appendix D: Master Constraints File Listing

    Appendix D Master Constraints File Listing The Xilinx design constraints (XDC) file template for the ZCU1285 board provides for designs targeting the Zynq UltraScale+ RFSoC ZCU1285 characterization kit. Net names in the listed constraints correlate with net names on the ZCU1285 board schematic. Identify the appropriate pins and replace the following net names with net names in the user RTL.

  • Page 63: Appendix E: System Controller

    Appendix E System Controller The Xilinx system controller is an application that runs on a Zynq-7000 SoC at power-up on the ZCU1285 board. The System Controller user interface (SCUI) can be downloaded from the Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit documentation page. The SCUI file rdf0513- zcu1285-system-controller-2019-1.zip is associated with this user guide.
  • Page 64 (see the following figure). On the left side of the window is the system controller controls and on the right side is a log of the operations. Figure 24: SCUI Main Window UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 65: Programmable Clocks Tab

    Appendix E: System Controller Connect a USB A to Micro-B USB cable from the host PC to the ZCU1285 USB/UART connector (callout 5, Figure 1-2). In the SCUI click File → Change the System Controller Port. In the Select the system controller port window, select the COM port associated with Silicon Labs Quad CP210x USB to UART Bridge: Interface 2, and press OK.
  • Page 66 Enter or click the related button (see the following figure). After the frequency is set, the Logging pane shows no errors and prints Finished. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 67 Enter to save the boot frequency to EEPROM (see the following figure). After the boot frequencies are set, the Logging pane shows no errors and prints Finished. Figure 29: CLK-101 Set Boot Frequency Tab UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 68 Click Read Si570 User Frequency to view the Si570 frequency and Last Set Si5368 User Frequency to view the Si5368 frequency (see the following figure). Figure 31: CLK-101 Last Set Tab UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 69 The SCUI is packaged with a set of clock files that contain register values for preset frequencies used by the SuperClock-RF2 clock sources. Each clock source has its own folder where the clock files are stored. The folders are located in BoardUI\tests\ZCU1285\clockFiles (see the following figure).
  • Page 70 Be sure to enter the exact file names from the associated folders. After the frequency is set, the Logging pane shows no errors and prints Finished. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 71 (see the following figure). After the boot frequencies are set, the Logging pane shows no errors and prints Finished. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 72 The last frequencies that were written to the CLK-103 Module can be viewed using the Last Set tab. Click the relevant last set button to view the last frequency written to the PLL by the SCUI (see the following figure). UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 73: Power Tab

    The SCUI can read the onboard INA226 power rail measurements for each of the power rails listed in the following table. The measurements can be read once or scanned continuously. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 74: Read A Single Power Rail

    To read a single power rail measurement, click the corresponding button with the power rail name on it. The power, voltage, and current measurements appear to the right of the button (see the following figure). UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 75: Read Multiple Power Rails

    Read Multiple Power Rails To read multiple power rail measurements at once, check the box to the left of each power rail button and click Run All (see the following figure). UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 76: Read Power Rails Continuously

    Select either the Run Continuously or Run x times, then click the power rail button to read the measurements. To stop the reading, click Terminate Running Operations (see the following figure). UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 77: Fmc Tab

    Power tab. Be sure to switch back to Run Once when using other tabs in the SCUI. Figure 41: Read Power Rails Continuously FMC Tab The ZCU1285 board provides two FPGA mezzanine card (FMC) ANSI/VITA 57.1 expansion interfaces, JA3 and JA4 (callout 53 and 54, Figure 2: Board Component Locations).
  • Page 78 IMPORTANT! Changing the bank voltage affects all banks connected to that bank voltage, not just the FMC interface. Confirm that any other I/Os being used on the ZCU1285 board are compatible with the new bank voltage. Note: Power cycling ZCU1285 reverts all bank voltage changes back to the default voltage levels.

  • Page 79: Eeprom Data Tab

    XM104 card connected to JA3. EEPROM Data Tab The ZCU1285 System Controller includes an EEPROM that is used to store board information. The information entered into the Board Information window that appears when the SCUI is launched (see the SCUI Board Information Window in Connecting the System Controller User Interface) can be stored to the EEPROM using the EEPROM Data tab.

  • Page 80: Write Board Eeprom Data

    Appendix E: System Controller Figure 45: EEPROM Data Write Board EEPROM Data To write EEPROM data, use the Set buttons highlighted in the following figure. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 81: Read Board Eeprom Data

    Appendix E: System Controller Figure 46: Set EEPROM Data Read Board EEPROM Data To read EEPROM data, use the Get buttons highlighted in the following figure. UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...
  • Page 82 Figure 47: Get EEPROM Data The Get EEPROM Data button opens a window displaying the full contents of the EEPROM memory (see the following figure). Figure 48: Get EEPROM Data Window UG1348 (v1.0) July 16, 2019 www.xilinx.com Send Feedback ZCU1285 Board User Guide...

  • Page 83: Appendix F: Additional Resources And Legal Notices

    • On Windows, select Start → All Programs → Xilinx Design Tools → DocNav. • At the Linux command prompt, enter docnav. Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs: •...

  • Page 84: References

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx UG1348 (v1.0) July 16, 2019 www.xilinx.com...
  • Page 85 IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for...

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