Xilinx ZCU106 User Manual page 143

#GPIO 8-POLE DIP SW
set_property PACKAGE_PIN A17
set_property IOSTANDARD
set_property PACKAGE_PIN A16
set_property IOSTANDARD
set_property PACKAGE_PIN B16
set_property IOSTANDARD
set_property PACKAGE_PIN B15
set_property IOSTANDARD
set_property PACKAGE_PIN A15
set_property IOSTANDARD
set_property PACKAGE_PIN A14
set_property IOSTANDARD
set_property PACKAGE_PIN B14
set_property IOSTANDARD
set_property PACKAGE_PIN B13
set_property IOSTANDARD
#GPIO LEDs
set_property PACKAGE_PIN AL11
set_property IOSTANDARD
set_property PACKAGE_PIN AL13
set_property IOSTANDARD
set_property PACKAGE_PIN AK13
set_property IOSTANDARD
set_property PACKAGE_PIN AE15
set_property IOSTANDARD
set_property PACKAGE_PIN AM8
set_property IOSTANDARD
set_property PACKAGE_PIN AM9
set_property IOSTANDARD
set_property PACKAGE_PIN AM10
set_property IOSTANDARD
set_property PACKAGE_PIN AM11
set_property IOSTANDARD
#PMOD
#PMOD0 RT. ANGLE RECEPTACLE 2X6
set_property PACKAGE_PIN B23
set_property IOSTANDARD
set_property PACKAGE_PIN A23
set_property IOSTANDARD
set_property PACKAGE_PIN F25
set_property IOSTANDARD
set_property PACKAGE_PIN E20
set_property IOSTANDARD
set_property PACKAGE_PIN K24
set_property IOSTANDARD
set_property PACKAGE_PIN L23
set_property IOSTANDARD
set_property PACKAGE_PIN L22
set_property IOSTANDARD
set_property PACKAGE_PIN D7
set_property IOSTANDARD
#PMOD1 MALE PIN HEADER 2X6
set_property PACKAGE_PIN AN8
set_property IOSTANDARD
set_property PACKAGE_PIN AN9
ZCU106 Board User Guide
UG1244 (v1.0) March 28, 2018
[get_ports "GPIO_DIP_SW0"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW0"] ;
[get_ports "GPIO_DIP_SW1"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW1"] ;
[get_ports "GPIO_DIP_SW2"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW2"] ;
[get_ports "GPIO_DIP_SW3"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW3"] ;
[get_ports "GPIO_DIP_SW4"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW4"] ;
[get_ports "GPIO_DIP_SW5"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW5"] ;
[get_ports "GPIO_DIP_SW6"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW6"] ;
[get_ports "GPIO_DIP_SW7"] ;
LVCMOS18 [get_ports "GPIO_DIP_SW7"] ;
[get_ports "GPIO_LED_0_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_0_LS"] ;
[get_ports "GPIO_LED_1_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_1_LS"] ;
[get_ports "GPIO_LED_2_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_2_LS"] ;
[get_ports "GPIO_LED_3_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_3_LS"] ;
[get_ports "GPIO_LED_4_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_4_LS"] ;
[get_ports "GPIO_LED_5_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_5_LS"] ;
[get_ports "GPIO_LED_6_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_6_LS"] ;
[get_ports "GPIO_LED_7_LS"] ;
LVCMOS12 [get_ports "GPIO_LED_7_LS"] ;
[get_ports "PMOD0_0_LS"] ;
LVCMOS18 [get_ports "PMOD0_0_LS"] ;
[get_ports "PMOD0_1_LS"] ;
LVCMOS18 [get_ports "PMOD0_1_LS"] ;
[get_ports "PMOD0_2_LS"] ;
LVCMOS18 [get_ports "PMOD0_2_LS"] ;
[get_ports "PMOD0_3_LS"] ;
LVCMOS18 [get_ports "PMOD0_3_LS"] ;
[get_ports "PMOD0_4_LS"] ;
LVCMOS18 [get_ports "PMOD0_4_LS"] ;
[get_ports "PMOD0_5_LS"] ;
LVCMOS18 [get_ports "PMOD0_5_LS"] ;
[get_ports "PMOD0_6_LS"] ;
LVCMOS18 [get_ports "PMOD0_6_LS"] ;
[get_ports "PMOD0_7_LS"] ;
LVCMOS18 [get_ports "PMOD0_7_LS"] ;
[get_ports "PMOD1_0_LS"] ;
LVCMOS12 [get_ports "PMOD1_0_LS"] ;
[get_ports "PMOD1_1_LS"] ;
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Appendix B: Master Constraints File Listing
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