Clock Generation - Xilinx VC707 User Manual

Clock Generation

The VC707 board provides five clock sources for the FPGA.
each clock.
Table 1-9: VC707 Board Clock Sources
Clock
Clock Name
Source
System Clock U51
User Clock U34
J31
User SMA Clock
(differential pair)
J32
J25
GTX SMA REF Clock
(differential pair)
J26
Jitter Attenuated
U24
Clock
Table 1-10
Table 1-10: Clock Connections, Source to FPGA
Clock Source Pin
U51.5
U51.4
U34.5
U34.4
J26.1
J25.1
J32.1
J31.1
U24.29
U24.28
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (SiTime).
See System Clock (SYSCLK_P and
2
Si570 3.3V LVDS I C Programmable Oscillator, 156.250 MHz default (Silicon Labs).
See Programmable User Clock (USER_CLOCK_P and
USER_SMA_CLOCK_P (Net name).
See User SMA Clock (USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N (Net name).
See User SMA Clock (USER_SMA_CLOCK_P and
SMA_MGT_REFCLK_C_P (Net name).
See GTX SMA Clock (SMA_MGT_REFCLK_P and
SMA_MGT_REFCLK_C_N (Net name).
See GTX SMA Clock (SMA_MGT_REFCLK_P and
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs).
See Jitter Attenuated Clock.
lists the pin-to-pin connections from each clock source to the FPGA.
Net Name
SYSCLK_N
SYSCLK_P
USER_CLOCK_N
USER_CLOCK_P
SMA_MGT_REFCLK_N
SMA_MGT_REFCLK_P
USER_SMA_CLOCK_N
USER_SMA_CLOCK_P
Si5324_OUT_N
Si5324_OUT_P
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Table 1-9
Description
SYSCLK_N).
USER_CLOCK_N).
USER_SMA_CLOCK_N).
USER_SMA_CLOCK_N).
SMA_MGT_REFCLK_N).
SMA_MGT_REFCLK_N).
I/O Standard
LVDS
LVDS
LVDS
LVDS
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
LVCMOS18
LVCMOS18
N/A (MGT REFCLK INPUT)
N/A (MGT REFCLK INPUT)
Feature Descriptions
lists the source devices for
FPGA (U1) Pin
E18
E19
AL34
AK34
AK7
AK8
AK32
AJ32
AD7
AD8
29
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