Interrupt Permission/Prohibition - Epson S1C17001 Technical Manual

6 INITERRUPT CONTROLLER

6.3.3 Interrupt Permission/Prohibition

Sending an interrupt request to the S1C17 core requires first permitting the individual interrupts using the interrupt
enable bit inside the ITC_EN register (0x4302) corresponding to the interrupt flag. Setting the interrupt enable bit
to 1 permits interrupts, while setting it to 0 (default) prohibits interrupts. The interrupt enable bit does not affect the
interrupt flag. Interrupt flags for interrupt requests generated by a peripheral module will be set regardless of the
interrupt enable bit setting.
Table 6.3.3.1 shows the correspondence between interrupt enable bits and interrupt flags.
Vector No. Hardware interrupt
4 P0 port interrupt
5 P1 port interrupt
6 Stopwatch timer interrupt
7 Clock timer interrupt
8 8-bit OSC1 timer interrupt
11 PWM & capture timer interrupt
12 8-bit timer interrupt
13 16-bit timer Ch.0 interrupt
14 16-bit timer Ch.1 interrupt
15 16-bit timer Ch.2 interrupt
16 UART interrupt
17 Remote controller interrupt
18 SPI interrupt
19 I 2 C interrupt
Note: • To prevent generating unnecessary interrupts, always set the interrupt flags before
permitting interrupts by writing 1 to the interrupt enable bit.
• To generate an actual interrupt, the IE bit in the S1C17 core Processor Status Register (PSR)
must be set to 1, in addition to the interrupt enable bit. The S1C17 core will not accept
maskable interrupt requests if the IE bit is set to 0. In this case, interrupt requests from the
ITC will be retained and accepted after the IE bit is set to 1.
32
Table 6.3.3.1: Interrupt enable bit list
Interrupt flag
EIFT0 (D0/ITC_IFLG register)
EIFT1 (D1/ITC_IFLG register)
EIFT2 (D2/ITC_IFLG register)
EIFT3 (D3/ITC_IFLG register)
EIFT4 (D4/ITC_IFLG register)
EIFT7 (D7/ITC_IFLG register)
IIFT0 (D8/ITC_IFLG register)
IIFT1 (D9/ITC_IFLG register)
IIFT2 (D10/ITC_IFLG register)
IIFT3 (D11/ITC_IFLG register)
IIFT4 (D12/ITC_IFLG register)
IIFT5 (D13/ITC_IFLG register)
IIFT6 (D14/ITC_IFLG register)
IIFT7 (D15/ITC_IFLG register)
EPSON
Interrupt enable bit
EIEN0 (D0/ITC_EN register)
EIEN1 (D1/ITC_EN register)
EIEN2 (D2/ITC_EN register)
EIEN3 (D3/ITC_EN register)
EIEN4 (D4/ITC_EN register)
EIEN7 (D7/ITC_EN register)
IIEN0 (D8/ITC_EN register)
IIEN1 (D9/ITC_EN register)
IIEN2 (D10/ITC_EN register)
IIEN3 (D11/ITC_EN register)
IIEN4 (D12/ITC_EN register)
IIEN5 (D13/ITC_EN register)
IIEN6 (D14/ITC_EN register)
IIEN7 (D15/ITC_EN register)
S1C17001 TECHNICAL MANUAL