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2
20 I
C
Transfer direction indicates the data transfer direction after the slave address. This is set to 0 when sending data
from the master to the slave and to 1 when receiving data from the slave.
Transmission is controlled as described below by setting the 8-bit data created as described above to the trans-
fer data register.
The slave address and transfer direction bits can be sent only once after generating the start condition. After the
slave address has been output, data can be sent and received as many times as required. Data must be sent or
received according to the transfer direction set together with the slave address.
Data transmission control
The procedure for transmitting data is described below. Slave address transmission involves the same proce-
dure.
To send byte data, set the transmission data to RTDT[7:0] (D[7:0]/I2C_DAT register). Set TXE (D9/I2C_DAT
register) to 1 to transmit 1 byte.
∗ RTDT[7:0]: Receive/Transmit Data Bits in the I
∗ TXE: Transmit Execution Bit in the I
When TXE is set to 1, the I
previous data is currently being transmitted, data transmission starts after this has been completed.
The I
2
C module first transfers the data written to the shift register, then starts outputting the clock from SCL.
Resetting TXE to 0 at this point generates an interrupt, enabling the subsequent transmission data and TXE to
be reset.
The data bits in the shift register are shifted in sequence at the clock falling edge and output via the SDA pin
with the MSB leading.
The I
2
C module outputs 9 clocks with each data transmission. In the 9th clock cycle, an ACK or NACK is re-
ceived from the slave device with the SDA signal as high impedance.
The slave device returns ACK(0) to the master if the data is received. If the data is not received, SDA is not
pulled down, which the I
SDA (output)
SDA (input)
SCL (output)
The I
2
C module includes two status bits, TBUSY (D8/I2C_CTL register) and RTACK (D8/I2C_DAT register),
for transmission control.
∗ TBUSY: Transmit Busy Flag in the I
∗ RTACK: Receive/Transmit ACK Bit in the I
The TBUSY flag indicates the data transmission status. This flag becomes 1 when transmission starts (including
slave address transmission) and reverts to 0 once data transmission ends. It also reverts to 0 for Wait state.
Inspect the flag to check whether the I
The RTACK bit indicates whether or not the slave device returned an ACK for the previous transmission.
RTACK is 0 if an ACK was returned and 1 if ACK was not returned.
254
2
C Data (I2C_DAT) Register (D9/0x4344)
2
C module begins data transmission in sync with the clock. If the start condition or
2
C module interprets to mean an NACK(1) (transmission failed).
D7
1
Start condition
Figure 20.5.3: ACK and NACK
2
C Control (I2C_CTL) Register (D8/0x4342)
2
C Data (I2C_DAT) Register (D8/0x4344)
C module is currently transmitting or at standby.
2
EPSON
2
C Data (I2C_DAT) Register (D[7:0]/0x4344)
D6
D0
2
ACK
NACK
8
9
S1C17001 TECHNICAL MANUAL
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