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0x5003: Clock Timer Interrupt Flag Register (CT_IFLG)
Register name Address
Bit
Clock Timer
0x5003
D7–4 –
Interrupt Flag
(8 bits)
D3
Register
D2
(CT_IFLG)
D1
D0
This register indicates the occurrence state of interrupt factors due to clock timer 32 Hz, 8 Hz, 2 Hz, and 1 Hz sig-
nals. If a clock timer interrupt occurs, identify the interrupt factor (frequency) by reading the interrupt flag in this
register. CTIF* are CT module interrupt flags corresponding to the individual 32 Hz, 8 Hz, 2 Hz, and 1 Hz inter-
rupts. It is set to 1 at the falling edge of each signal if CTIE* (CT_IMSK register) is set to 1. The clock timer inter-
rupt request signal is output to the ITC at the same time. This interrupt request signal sets the clock timer interrupt
flag in the ITC to 1 and generates an interrupt if the ITC and S1C17 core interrupt conditions are met.
The following processes must be performed to manage the interrupt factor occurrence state using this register.
1. Set the ITC clock timer interrupt trigger mode to level trigger mode.
2. Reset the CT module interrupt flag within the interrupt processing routine after the interrupt occurs (this also re-
sets the ITC interrupt flag).
CTIF* is reset by writing as 1.
Note: To prevent generating unnecessary interrupts, CTIF* must be reset before permitting clock
timer interrupts using CTIE.*
D3
CTIF32: 32 Hz Interrupt Flag
Interrupt flag indicating the 32 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting CTIE32 (D3/CT_IMSK register) to 1 sets CTIF32 to 1 at the 32 Hz signal falling edge.
D2
CTIF8: 8 Hz Interrupt Flag
Interrupt flag indicating the 8 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting CTIE8 (D2/CT_IMSK register) to 1 sets CTIF8 to 1 at the 8 Hz signal falling edge.
D1
CTIF2: 2 Hz Interrupt Flag
Interrupt flag indicating the 2 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting CTIE2 (D1/CT_IMSK register) to 1 sets CTIF2 to 1 at the 2 Hz signal falling edge.
D0
CTIF1: 1 Hz Interrupt Flag
Interrupt flag indicating the 1 Hz interrupt factor occurrence status.
1(R):
Interrupt factor present
0(R):
No interrupt factor (default)
1(W):
Reset flag
0(W):
Disabled
Setting CTIE1 (D0/CT_IMSK register) to 1 sets CTIF1 to 1 at the 1 Hz signal falling edge.
S1C17001 TECHNICAL MANUAL
Name
Function
reserved
CTIF32
32 Hz interrupt flag
CTIF8
8 Hz interrupt flag
CTIF2
2 Hz interrupt flag
CTIF1
1 Hz interrupt flag
EPSON
Setting
Init. R/W
–
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
15 CLOCK TIMER (TC)
Remarks
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R/W
187
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