Uart Interrupts - Epson S1C17001 Technical Manual

18.7 UART Interrupts

The UART includes a function for generating the following three different interrupt types.
• Transmit buffer empty interrupt
• Receive buffer full interrupt
• Receive error interrupt
The UART outputs one interrupt signal shared by the three above interrupt factor types to the interrupt controller
(ITC). Inspect the status flag or error flag to determine the interrupt factor occurring.
Transmit buffer empty interrupt
To use this interrupt, set TIEN (D4/UART_CTL register) to 1. If TIEN is set to 0 (default), interrupt requests
for this factor will not be sent to the ITC.
∗ TIEN: Transmit Buffer Empty Interrupt Enable Bit in the UART Control (UART_CTL) Register (D4/0x4104)
When transmission data written to the transmit data buffer is transferred to the shift register, the UART sets
the TDBE bit (D0/UART_ST register) to 1, indicating that the transmit data buffer is empty. If transmit buffer
empty interrupts are permitted (TIEN = 1), an interrupt request pulse is sent simultaneously to the ITC.
∗ TDBE: Transmit Data Buffer Empty Flag in the UART Status (UART_ST) Register (D0/0x4100)
An interrupt occurs if other interrupt conditions are met.
You can inspect the TDBE flag in the UART interrupt processing routine to determine whether the UART in-
terrupt is attributable to a transmit buffer empty. If TDBE is 0, the next transmission data can be written to the
transmit data buffer by the interrupt processing routine.
Receive buffer full interrupt
To use this interrupt, set RIEN (D5/UART_CTL register) to 1. If RIEN is set to 0 (default), interrupt requests
for this factor will not be sent to the ITC.
∗ RIEN: Receive Buffer Full Interrupt Enable Bit in the UART Control (UART_CTL) Register (D5/0x4104)
If the specified volume of received data is loaded into the receive data buffer when a receive buffer full inter-
rupt is permitted (RIEN = 1), the UART outputs an interrupt request pulse to the ITC. If RBFI (D1/UART_CTL
register) is 0, an interrupt request pulse is output as soon as one item of received data is loaded into the receive
data buffer (RDRY flag (D1/UART_ST register) is set to 1). If RBFI (D1/UART_CTL register) is 1, an inter-
rupt request pulse is output as soon as two items of received data are loaded into the receive data buffer (RD2B
flag (D3/UART_ST register) is set to 1).
∗ RBFI: Receive Buffer Full Interrupt Condition Setup Bit in the UART Control (UART_CTL) Register (D1/0x4104)
∗ RDRY: Receive Data Ready Flag in the UART Status (UART_ST) Register (D1/0x4100)
∗ RD2B: Second Byte Receive Flag in the UART Status (UART_ST) Register (D3/0x4100)
An interrupt occurs if other interrupt conditions are met.
You can inspect the RDRY and RD2B flags in the UART interrupt processing routine to determine whether the
UART interrupt is attributable to a receive buffer full. If RDRY or RD2B is 1, the received data can be read
from the receive data buffer by the interrupt processing routine.
S1C17001 TECHNICAL MANUAL
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