Cpu Core Clock (Cclk) Control - Epson S1C17001 Technical Manual

8 CLOCK GENERATOR (CLG)

8.2 CPU Core Clock (CCLK) Control

The CLG module incorporates a clock gear to slow down the system clock to send to the S1C17 core. To reduce
power consumption, operate the S1C17 core with the slowest possible clock speed. The halt command can be ex-
ecuted to stop the clock feed from the CLG to the S1C17 core for power savings.
OSC3
System clock
OSC1
Clock gear settings
CCLKGR[1:0] (D[1:0]/CLG_CCLK register) is used to select the gear ratio to reduce system clock speeds.
∗ CCLKGR[1:0]: CCLK Clock Gear Ratio Select Bits in the CCLK Control (CLG_CCLK) Register (D[1:0]/0x5081)
Clock feed control
The CCLK clock feed is stopped by executing the halt command. Since this does not stop the system clock, pe-
ripheral modules will continue to operate.
HALT mode is cleared by resetting, NMI, or other interrupts. The CCLK feed resumes when HALT mode is
cleared.
Executing the slp command suspends system clock feed to the CLG, thereby halting the CCLK feed as well.
Clearing SLEEP mode with an external interrupt restarts the system clock feed and the CCLK feed.
For more information on system clock control, refer to "7. Oscillator Circuit (OSC)."
72
Gear selection
Cock gear
(1/1 to 1/8)
Figure 8.2.1: CCLK feed system
Table 8.2.1: CCLK gear ratio selection
CCLKGR[1:0]
0x3
0x2
0x1
0x0
EPSON
HALT
Gate
CCLK
Gear ratio
1/8
1/4
1/2
1/1
(Default: 0x0)
S1C17001 TECHNICAL MANUAL
S1C17 core