Watchdog Timer (Wdt); Watchdog Timer Overview - Epson S1C17001 Technical Manual

17 Watchdog Timer (WDT)

17.1 Watchdog Timer Overview

The S1C17001 incorporates a watchdog timer that uses the OSC1 oscillator circuit as its oscillation source. The
watchdog timer generates an NMI or reset (selectable via software) to the CPU if not reset within 131,072/f
seconds (4 seconds when f
Reset the watchdog timer via software within this cycle to prevent NMI/resets, which in turn enables runaway de-
tection for programs that do not pass through the processing routine.
Figure 17.1.1 illustrates the watchdog timer block diagram.
OSC
OSC1 oscillation/
256Hz
division circuit
Reset
NMI
S1C17001 TECHNICAL MANUAL
= 32.768 kHz).
OSC1
WDTRUN[3:0]
Run/Stop control
Figure 17.1.1: Watchdog timer block diagram
WDTRST
Watchdog timer reset
10-bit counter
Interrupt
control circuit
EPSON
17 WATCHDOG TIMER (WDT)
Watchdog timer
NMI/Reset mode
WDTMD
selection
OSC1
203