0X4346: I 2 C Interrupt Control Register (I2C_Ictl) - Epson S1C17001 Technical Manual

2
0x4346: I C Interrupt Control Register (I2C_ICTL)
Register name Address Bit
I 2 C Interrupt 0x4346 D15–2 –
Control Register (16 bits)
D1
(I2C_ICTL)
D0
D[15:2] Reserved
D1 RINTE: Receive Interrupt Enable Bit
Permits or prohibits receive buffer full I
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Setting RINTE to 1 permits the output of I
full. These interrupt requests are generated when the data received in the shift register is transferred to
RTDT[7:0] (D[7:0]/I2C_DAT register) (when receipt is complete).
I 2 C interrupts are not generated by receive data buffer full if RINTE is set to 0.
D0 TINTE: Transmit Interrupt Enable Bit
Permits or prohibits transmit buffer empty I
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Setting TINTE to 1 permits the output of I
empty. These interrupt requests are generated when the data written to RTDT[7:0] (D[7:0]/I2C_DAT
register) is transferred to the shift register.
I 2 C interrupts are not generated by transmit buffer empty if TINTE is set to 0.
S1C17001 TECHNICAL MANUAL
Name Function
reserved
RINTE Receive interrupt enable
TINTE Transmit interrupt enable
C interrupts.
2
EPSON
Setting
–
1 Enable 0 Disable
1 Enable 0 Disable
2 C interrupt requests to the ITC due to a receive data buffer
2 C interrupts.
C interrupt requests to the ITC due to a transmit buffer
2
2
20 I C
Init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W
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