Core I/O Reserved Area - Epson S1C17001 Technical Manual

3.5 Core I/O Reserved Area

The 1 Kbyte area from 0xfffc00 to 0xffffff is used as the CPU core I/O area, and the following I/O registers are as-
signed.
Peripheral circuit Address
S1C17 core I/O
0xffff80
0xffff84
0xffff90
For more information on TTBR, refer to "2.4 Vector Table"; and for more information on IDIR, refer to "2.5 Pro-
cessor Information."
For more information on DBRAM, refer to "22 On-chip Debugging (DBG)."
S1C17001 TECHNICAL MANUAL
Table 3.5.1: I/O map (Core I/O reserved area)
Register name
TTBR Vector Table Base Register
IDIR Processor ID Register
DBRAM Debug RAM Base Register
EPSON
3 MEMORY MAP AND BUS CONTROL
Function
Vector table base address display
Processor ID display
Debugging RAM base address display
21