0X5040: Watchdog Timer Control Register (Wdt_Ctl) - Epson S1C17001 Technical Manual

0x5040: Watchdog Timer Control Register (WDT_CTL)

Register name Address Bit
Watchdog 0x5040 D7–5 –
Timer Control (8 bits)
D4
Register D3–0 WDTRUN[3:0] Watchdog timer run/stop control Other than 1010
(WDT_CTL)
D[7:5] Reserved
D4 WDTRST: Watchdog Timer Reset Bit
Resets the watchdog timer.
1 (W): Reset
0 (W): Disabled
0 (R): Normally 0 when read out (default)
To use the watchdog timer, it must be reset by writing 1 to this bit within the NMI/Reset generation
cycle (4 seconds when f
This resets the up-counter to 0 and starts counting with a new NMI/Reset generation cycle.
D[3:0] WDTRUN[3:0]: Watchdog Timer Run/Stop Control Bits
Controls the watchdog timer Run/Stop.
Values other than 0b1010 (R/W): Run
0b1010 (R/W):
The watchdog timer must also be reset to prevent generation of an unnecessary NMI or Reset while the
watchdog timer operates.
S1C17001 TECHNICAL MANUAL
Name Function
reserved
WDTRST Watchdog timer reset
= 32.768 kHz).
OSC1
Stop (default)
EPSON
17 WATCHDOG TIMER (WDT)
Setting Init. R/W
–
1 Reset 0 Ignored
1010 1010 R/W
Run Stop
Remarks
– – 0 when being read.
0 W
207