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0x5000–0x5003
Register name Address
Bit
Clock Timer
0x5000
D7–5 –
Control Register
(8 bits)
D4
(CT_CTL)
D3–1 –
D0
Clock Timer
0x5001
D7–0 CTCNT[7:0] Clock timer counter value
Counter Register
(8 bits)
(CT_CNT)
Clock Timer
0x5002
D7–4 –
Interrupt Mask
(8 bits)
D3
Register
D2
(CT_IMSK)
D1
D0
Clock Timer
0x5003
D7–4 –
Interrupt Flag
(8 bits)
D3
Register
D2
(CT_IFLG)
D1
D0
S1C17001 TECHNICAL MANUAL
Name
Function
reserved
CTRST
Clock timer reset
reserved
CTRUN
Clock timer run/stop control
reserved
CTIE32
32 Hz interrupt enable
CTIE8
8 Hz interrupt enable
CTIE2
2 Hz interrupt enable
CTIE1
1 Hz interrupt enable
reserved
CTIF32
32 Hz interrupt flag
CTIF8
8 Hz interrupt flag
CTIF2
2 Hz interrupt flag
CTIF1
1 Hz interrupt flag
EPSON
APPENDIX A I/O REGISTER LIST
Setting
Init. R/W
–
1 Reset
0 Ignored
–
1 Run
0 Stop
0x0 to 0xff
–
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
1 Enable
0 Disable
–
1 Cause of
0 Cause of
interrupt
interrupt not
occurred
occurred
Clock Timer
Remarks
–
–
0 when being read.
0
W
–
–
0
R/W
0
R
–
–
0 when being read.
0
R/W
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W Reset by writing 1.
0
R/W
0
R/W
0
R/W
317
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