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0x4320: SPI Status Register (SPI_ST)
Register name Address
Bit
SPI Status Reg-
0x4320
D15–3 –
ister
(16 bits)
D2
(SPI_ST)
D1
D0
D[15:3]
Reserved
D2
SPBSY: Transfer Busy Flag (Master Mode)/ss Signal Low Flag (Slave Mode)
Master mode
Indicates the SPI transfer status.
1 (R):
Operating
0 (R):
Standby (default)
SPBSY is set to 1 when the SPI starts data transfer in Master mode and is maintained at 1 while transfer
is underway.
It is cleared to 0 once the transfer is complete.
Slave mode
Indicates the slave selection (#SPISS) signal status.
1 (R):
Low level (this SPI is selected)
0 (R):
High level (this SPI is not selected) (default)
SPBSY is set to 1 when the master device sets the #SPISS signal to active to select this SPI module
(slave device). It is returned to 0 when the master device clears the SPI module selection by returning
the #SPISS signal to inactive.
D1
SPRBF: Receive Data Buffer Full Flag
Indicates the receive data buffer status.
1 (R):
Data full
0 (R):
No data (default)
SPRBF is set to 1 when data received in the shift register is sent to the receive data buffer (when receiv-
ing is complete), indicating that the data can be read. It reverts to 0 once the buffer data is read from the
SPI_RXD register (0x4324).
D0
SPTBE: Transmit Data Buffer Empty Flag
Indicates the state of the transmit data buffer.
1 (R):
Empty (default)
0 (R):
Data exists
SPTBE is set to 0 when transmit data is written to the SPI_TXD register (transmit data buffer, 0x4322),
and is set to 1 when the data is transferred to the shift register (when transmission starts).
Transmission data is written to the SPI_TXD register when this bit is 1.
S1C17001 TECHNICAL MANUAL
Name
Function
reserved
SPBSY
Transfer busy flag (master)
ss signal low flag (slave)
SPRBF
Receive data buffer full flag
SPTBE
Transmit data buffer empty flag
EPSON
Setting
Init. R/W
–
1 Busy
0 Idle
1 ss = L
0 ss = H
1 Full
0 Not full
1 Empty
0 Not empty
19 SPI
Remarks
–
–
0 when being read.
0
R
0
R
1
R
243
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