Clock Timer Run/Stop Control - Epson S1C17001 Technical Manual

15 CLOCK TIMER (TC)

15.4 Clock Timer RUN/STOP Control

Set the following items before starting the clock timer.
(1) If using interrupts, set the interrupt level and permit interrupts for the clock timer. See Section 15.5.
(2) Reset the timer. See Section 15.3.
The clock timer includes CTRUN (D0/CT_CTL register) to control Run/Stop.
∗ CTRUN: Clock Timer Run/Stop Control Bit in the Clock Timer Control (CT_CTL) Register (D0/0x5000)
The clock timer starts operating when CTRUN is written as 1. Writing 0 to CTRUN prevents clock input and stops
the operation.
This control does not affect the counter (CT_CNT register) data. The counter data is retained even when the count
is halted, allowing resumption of the count from that data.
If CTRUN and CTRST are written as 1 simultaneously, the clock timer starts counting after the reset.
Interrupt factors are generated during counting at the corresponding 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling
edges. If interrupts are permitted, interrupt requests are sent to the interrupt controller (ITC).
OSC1-1/128 256Hz
CTCNT0 128Hz
CTCNT1 64Hz
CTCNT2 32Hz
CTCNT3 16Hz
CTCNT4 8Hz
CTCNT5 4Hz
CTCNT6 2Hz
CTCNT7 1Hz
32 Hz interrupt
8 Hz interrupt
2 Hz interrupt
1 Hz interrupt
Note: The clock timer switches to Run/Stop mode when data is written to CTRUN synchronized
with the 256 Hz signal falling edge. When 0 is written to CTRUN, the timer switches to Stop
state after counting an additional "+1." 1 is retained for CTRUN reading until the timer actually
stops.
Figure 15.4.2 shows the Run/Stop control timing chart.
180
Figure 15.4.1: Clock timer timing chart
256Hz
CTRUN(RD)
CTRUN(WR)
CT_CNT register 0x57
Figure 15.4.2: Run/Stop control timing chart
0x58 0x59 0x5a 0x5b
EPSON
0x5c
S1C17001 TECHNICAL MANUAL