0X5080-0X5081; Clock Generator - Epson S1C17001 Technical Manual

0x5080–0x5081
Register name Address Bit
PCLK Control 0x5080 D7–2 –
Register (8 bits)
D1–0 PCKEN[1:0] PCLK enable
(CLG_PCLK)
CCLK Control 0x5081 D7–2 –
Register (8 bits)
D1–0 CCLK-
(CLG_CCLK)
S1C17001 TECHNICAL MANUAL
Name Function
reserved
reserved
CCLK clock gear ratio select
GR[1:0]
EPSON
APPENDIX A I/O REGISTER LIST
Setting Init. R/W
– –
PCKEN[1:0] PCLK supply 0x3 R/W
0x3 Enable
0x2 Not allowed
0x1 Not allowed
0x0 Disable
– –
CCLKGR[1:0] Gear ratio 0x0 R/W
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1

Clock Generator

Remarks
– 0 when being read.
– 0 when being read.
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