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9. Prescaler (PSC)
9.1 Prescaler Configuration
The S1C17001 incorporates a prescaler to generate a clock for timer operations. The prescaler generates 15 differ-
ent frequencies by dividing the PCLK clock fed from the clock generator into 1/1 to 1/16K. The peripheral modules
to which the clock is fed include clock selection registers enabling selection of one as a count or operation clock.
PSC
PCLK
Debug status
signal
The prescaler is controlled by the PRUN bit (D0/PSC_CTL register). To operate the prescaler, write 1 to PRUN.
Writing 0 to PRUN stops the prescaler. Stopping the prescaler while the timer and interface module are halted en-
ables the current consumption to be reduced. The prescaler is stopped immediately after initial resetting.
∗ PRUN: Prescaler Run/Stop Control Bit in the Prescaler Control (PSC_CTL) Register (D0/0x4020)
Note: PCLK must be fed from the clock generator to use the prescaler.
The prescaler features another control bit, PRUND (D1/PSC_CTL register), which specifies prescaler operations
in Debug mode. Setting PRUND to 1 also operates the prescaler in Debug mode. Setting it to 0 stops the prescaler
once the S1C17 core switches to Debug mode. Set PRUND to 1 if the timer and interface module are to be used
during debugging.
∗ PRUND: Prescaler Run/Stop Setting Bit in Debug Mode in the Prescaler Control (PSC_CTL) Register (D1/0x4020)
S1C17001 TECHNICAL MANUAL
1/1
1/2
1/4
1/8
1/16 1/32 1/64 1/128
1/256 1/512 1/1K 1/2K 1/4K 1/8K 1/16K
Figure 9.1.1: Prescaler
8-bit timer
16-bit timer Ch.0
16-bit timer Ch.1
16-bit timer Ch.2
PWM & capture timer
Remote controller
P port
EPSON
9 PRESCALER (PSC)
UART
SPI
2
I
C
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