Clock Timer Interrupts - Epson S1C17001 Technical Manual

15.5 Clock Timer Interrupts

The CT module includes functions for generating the following four kinds of interrupts:
32 Hz, 8 Hz, 2 Hz, 1 Hz interrupts
The CT module outputs a single interrupt signal shared by the above four interrupt factors to the interrupt controller
(ITC). The interrupt flag within the CT module should be read to identify the interrupt factor that occurred.
32 Hz, 8 Hz, 2 Hz, 1 Hz interrupts
Generated at the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling edges, these interrupt requests set the following in-
terrupt flags in the CT module to 1.
∗ CTIF32: 32 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D3/0x5003)
∗ CTIF8:
8 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D2/0x5003)
∗ CTIF2:
2 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D1/0x5003)
∗ CTIF1:
1 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D0/0x5003)
To use these interrupts, set the following interrupt enable bits to 1 for the corresponding interrupt flags. If the
interrupt enable bits are set to 0 (default), the interrupt flag will not be set to 1, and the interrupt requests for
this factor will not be sent to the ITC.
∗ CTIE32: 32 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D3/0x5002)
∗ CTIE8:
8 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D2/0x5002)
∗ CTIE2:
2 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D1/0x5002)
∗ CTIE1:
1 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D0/0x5002)
The CT module outputs an interrupt request to the ITC if the CTIF* is set to 1. This interrupt request signal sets
the clock timer interrupt flag inside the ITC to 1 and generates an interrupt if the ITC and S1C17 core interrupt
conditions are met.
Check the frequency of a clock timer interrupt by reading CTIF* as part of the clock timer interrupt processing
routine.
The interrupt factor should be cleared with the interrupt processing routine by resetting the CT module CTIF* (to
1) rather than the clock timer interrupt flag.
Note: To prevent generating unnecessary interrupts, reset the corresponding CTIF* before permitting
clock timer interrupts from CTIE*.
Clock timer interrupt ITC register
The clock timer outputs an interrupt signal to the ITC using the falling edge for the frequency for which inter-
rupts are permitted in the settings previously described. To generate clock timer interrupts, the interrupt level
and interrupt permission should be set in the ITC register.
The clock timer ITC control bits are shown below.
Interrupt flag inside ITC
∗ EIFT3: Clock Timer Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D3/0x4300)
Interrupt enable bit inside ITC
∗ EIEN3: Clock Timer Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D3/0x4302)
Interrupt level setting bit inside ITC
∗ EILV3[2:0]: CT Interrupt Level Bits in the External Interrupt Level Setup (ITC_ELV1) Register 1
(D[10:8]/0x4308)
Interrupt trigger mode selection bit inside ITC (Fix at 1)
∗ EITG3: CT Interrupt Trigger Mode Select Bit in the External Interrupt Level Setup (ITC_ELV1) Register 1
(D12/0x4308)
S1C17001 TECHNICAL MANUAL
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15 CLOCK TIMER (TC)
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