Appendix B Power Saving; Clock Control Power Saving - Epson S1C17001 Technical Manual

Appendix B: Power Saving
Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and
the peripheral circuits being operated. Listed below are the control methods for saving power.
B.1 Clock Control Power Saving
Figure B.1.1 illustrates the S1C17001 clock system.
SLEEP, On/Off control
OSC3
OSC3
oscillator circuit
(8.2MHz)
OSC4
FOUT3
FOUT3
output circuit
On/Off control
SLEEP, On/Off control
OSC1
OSC1
oscillator circuit
(32.768kHz)
OSC2
FOUT1
FOUT1
output circuit
On/Off control
Noise filter
RESET
On/Off control
Noise filter
NMI
On/Off control
S1C17001 TECHNICAL MANUAL
OSC
Clock source
wakeup
selection
System
Wakeup OSC3
clock
wait circuit
OSC1
Division circuit
(1/1 to 1/4)
Division ratio
selection
S1C17 core
S1C17 core
Figure B.1.1 Clock system
Gear selection
Clock gear Gate
(1/1 to 1/8)
Gate
On/Off control
Gate
On/Off control
Gate Division circuit
(1/1 to 1/16K)
Division
OSC1
(1/128)
circuit
Gate
(1/1 to 1/32)
Division ratio selection On/Off control
EPSON

APPENDIX B POWER SAVING

CLG
HALT
CCLK S1C17 core
BCLK Internal bus, RAM,
ROM
HALT
ITC, T16, T8F, UART,
SPI, I2C, T16E, P,
PCLK
MISC, REMC,
Control resistor (CT,
SWT, WDT, T8OSC1)
PSC
T8F, T16, T16E,
REMC, P, UART, SPI,
I2C
CLK_256Hz CT, SWT, WDT
T8OSC1
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