Epson S1C17001 Technical Manual page 340

The peripheral modules listed below are operated by clocks other than PCLK, except for control register ac-
cess.
This means PCLK is not required after the control register has been set and operation started.
• Clock timer
• Stopwatch timer
• Watchdog timer
• 8-bit OSC1 timer
Maskable interrupts do not occur while PCLK is stopped. Interrupts are retained until the PCLK feed is re-
started.
Table B.1.1 shows a list of methods for clock control and starting/stopping the CPU.
Current
OSC1
consumption
Stop
Low
Oscillation
(system CLK)
Oscillation
(system CLK)
Oscillation
Oscillation
Oscillation
High
Oscillation
Canceling HALT and SLEEP modes (CPU startup methods)
1. Port startup
Started by input/output port interrupt factors or debug interrupts (ICD forced breaking). If the interrupt control-
ler or CPU IE flag blocks input/output port interrupts, the CPU executes commands following the halt or slp
commands without accepting the interrupt. If interrupts are permitted and PCLK was running before the halt
or slp commands were executed, the CPU branches to an interrupt processing routine. If PCLK was stopped
before the halt or slp commands were executed, branching to the interrupt processing routine is retained
until PCLK runs, even when interrupts are permitted.
2. OSC1 peripheral circuit startup
Started by clock timer, stopwatch timer, watchdog timer, or 8-bit OSC1 timer interrupt factors. If the interrupt
controller or CPU IE flag blocks these interrupts, the CPU executes commands following the halt command
without accepting the interrupt. If interrupts are permitted and PCLK was running before the halt command
was executed, the CPU branches to an interrupt processing routine. If PCLK was stopped before the halt
command was executed, branching to the interrupt processing routine is retained until PCLK runs, even when
interrupts are permitted.
3. PCLK peripheral circuit startup
Started by PCLK peripheral circuit interrupt factors permitted by the interrupt controller. If the CPU IE flag is 0,
the CPU executes commands following the halt command, rejecting the interrupt. If the IE flag is 1, the CPU
branches to an interrupt processing routine.
S1C17001 TECHNICAL MANUAL
Table B.1.1: Clock control list
OSC3 CPU (CCLK)
Stop Stop
Stop Stop
Stop Stop
Stop Operation(1/1)
Oscillation
Stop
(system CLK)
Oscillation Operation
(system CLK) (Low gear)
Oscillation
Operation(1/1)
(system CLK)
PCLK OSC1
peripheral peripheral
Stop Stop
Stop Operation
Operation Operation
Operation Operation
Operation Operation
Operation Operation
Operation Operation
EPSON
APPENDIX B POWER SAVING
CPU stop CPU startup
method method
Execute slp
1
command
Execute halt
1, 2
command
Execute halt
1, 2, 3
command
Execute halt
1, 2, 3
command
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