Spi Clock - Epson S1C17001 Technical Manual

19 SPI

19.3 SPI Clock

The Master mode SPI uses the internal clock output by the 16-bit timer Ch.1 as the SPI clock. This clock is output
from the SPICLK pin to the slave device while also driving the shift register. It should be programmed to output a
clock matching the transfer rate from the 16-bit timer Ch.1. For detailed information on 16-bit timer control, refer
to "11 16-bit Timer (T16)."
PCLK
16-bit timer Ch.1 underflow signal
SPI clock (SPICLK output)
Figure 19.3.1: Master mode SPI clock
In Slave mode, the SPI clock is input via the SPICLK pin. Since the internal circuit operates in sync with the PCLK
clock, the input clock is used to synchronize the differentiated PCLK clock.
Note: The frequency of the clock input via the SPICLK pin must be less than 1/3 of the PCLK and
have a clock duty ratio of 50%.
PCLK
SPICLK input
SPICLK differentiated signal
SPI clock (internal use)
Figure 19.3.2: Slave mode SPI clock
EPSON
S1C17001 TECHNICAL MANUAL 235