Memory Map And Bus Control - Epson S1C17001 Technical Manual

3 Memory Map and Bus Control

Figure 3.1 shows the S1C17001 memory map.
0xff ffff
Core I/O reserved area
(1 Kbyte, 1 cycle)
0xff fc00
0xff fbff
0x01 0000
0x00 ffff
Internal ROM area
(32 Kbytes, 1-5 cycles)
(Device size: 16 bits)
Vector table
0x00 8000
0x00 7fff
0x00 6000
0x00 5fff
Internal peripheral circuit area 2
(4 Kbytes, 3 cycles)
0x00 5000
0x00 4fff
0x00 4400
0x00 43ff
Internal peripheral circuit area 1
(1 Kbyte, 1 cycle)
0x00 4000
0x00 3fff
0x00 0800
0x00 07ff
Debug RAM area (64 bytes)
0x00 07c0
Internal RAM area
(2 Kbytes, 1 cycle)
(Device size: 32 bits)
0x00 0000
S1C17001 TECHNICAL MANUAL
reserved
reserved
reserved
reserved
Figure 3.1: S1C17001 memory map
3 MEMORY MAP AND BUS CONTROL
Peripheral functions
reserved
0x5360~0x5fff
Remote controller
0x5340~0x535f
MISC register
0x5320~0x533f
PWM & capture timer
0x5300~0x531f
reserved
0x52c0~0x52ff
Port MUX
0x52a0~0x52bf
reserved
0x5280~0x529f
P port
0x5200~0x527f
reserved
0x50e0~0x51ff
8-bit OSC1 timer
0x50c0~0x50df
reserved
0x50a0~0x50bf
Clock generator
0x5080~0x509f
Oscillator circuit
0x5060~0x507f
Watchdog timer
0x5040~0x505f
Stopwatch timer
0x5020~0x503f
Clock timer
0x5000~0x501f
reserved
0x4360~0x43ff
2
I
0x4340~0x435f
SPI
0x4320~0x433f
Interrupt controller
0x4300~0x431f
reserved
0x4280~0x42ff
16-bit timer Ch.2
0x4260~0x427f
16-bit timer Ch.1
0x4240~0x425f
16-bit timer Ch.0
0x4220~0x423f
8-bit timer
0x4200~0x421f
reserved
0x4120~0x41ff
UART
0x4100~0x411f
reserved
0x4040~0x40ff
Prescaler
0x4020~0x403f
reserved
0x4000~0x401f
EPSON
(Device size)
_
(8 bits)
(8 bits)
(16 bits)
_
(8 bits)
_
(8 bits)
_
(8 bits)
_
(8 bits)
(8 bits)
(8 bits)
(8 bits)
(8 bits)
(16 bits)
C (16 bits)
(16 bits)
(16 bits)
(16 bits)
(16 bits)
(16 bits)
(16 bits)
(16 bits)
(8 bits)
(8 bits)
(8 bits)
(8 bits)
(8 bits)
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