X4105: Uart Expansion Register (Uart_Exp) - Epson S1C17001 Technical Manual

18 UART

0x4105: UART Expansion Register (UART_EXP)

Register name Address Bit
UART 0x4105 D7
Expansion (8 bits)
D6–4 IRCLK[2:0] IrDA receive detection clock
Register
(UART_EXP)
D3–1 –
D0
D7 Reserved
D[6:4] IRCLK[2:0]: IrDA Receive Detection Clock Select Bits
Select the prescaler output clock used as the IrDA input pulse detection clock.
This clock must be selected as a clock faster than the 8-bit timer or transfer clock sclk input via the
SCLK pin.
The demodulation circuit treats Low pulses with a width of at least 2 IrDA receive detection clock
cycles as valid. Select the appropriate prescaler output clock to enable detection of input pulses with a
minimum width of 1.41 μs.
D[3:1] Reserved
D0 IRMD: IrDA Mode Select Bit
Switches the IrDA interface function on and off.
1 (R/W): On
0 (R/W): Off (default)
Set this to 1 to use the IrDA interface. When this bit is set to 0, this module functions as a normal
UART, with no IrDA functions.
230
Name Function
– reserved
select
reserved
IRMD IrDA mode select
Table 18.9.2: IrDA receive detection clock selection
IRCLK[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Setting
–
IRCLK[2:0]
0x7 PCLK-1/128
0x6 PCLK-1/64
0x5 PCLK-1/32
0x4 PCLK-1/16
0x3
0x2
0x1
0x0
–
1 On 0 Off
Prescaler output clock
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)
EPSON
Init. R/W Remarks
– – 0 when being read.
Clock 0x0 R/W
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
– – 0 when being read.
0 R/W
S1C17001 TECHNICAL MANUAL