Control Register Details - Epson S1C17001 Technical Manual

8 CLOCK GENERATOR (CLG)

8.4 Control Register Details

Address
0x5080 CLG_PCLK PCLK Control Register
0x5081 CLG_CCLK CCLK Control Register
The CLG module registers are described in detail below. These are 8-bit registers.
Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
74
Table 8.4.1 CLG register list
Register name
PCLK feed control
CCLK division ratio setting
EPSON
Function
S1C17001 TECHNICAL MANUAL