Epson S1C17001 Technical Manual page 229

18 UART
Receive error interrupt
To use this interrupt, set REIEN (D6/UART_CTL register) to 1. If REIEN is set to 0 (default), interrupt re-
quests will not be sent to the ITC for this factor.
∗ REIEN: Receive Error Interrupt Enable Bit in the UART Control (UART_CTL) Register (D6/0x4104)
The UART sets the error flags shown below to 1 if a parity error, framing error, or overrun error is detected
when receiving data. If receive error interrupts are permitted (REIEN = 1), an interrupt request pulse is output
at the same time to the ITC.
∗ PER: Parity Error Flag in the UART Status (UART_ST) Register (D5/0x4100)
∗ FER: Framing Error Flag in the UART Status (UART_ST) Register (D6/0x4100)
∗ OER: Overrun Error Flag in the UART Status (UART_ST) Register (D4/0x4100)
If other interrupt conditions are satisfied, an interrupt occurs.
Inspect the error flags above as part of the UART interrupt processing routine to determine whether the UART
interrupt was caused by a receive error. If any of the error flags has the value 1, the interrupt processing routine
will proceed with error recovery.
UART interrupt ITC registers
The UART ITC control bits are listed below.
Interrupt flag
∗ IIFT4: UART Interrupt Flag in the Interrupt Flag (ITC_IFLG) Register (D12/0x4300)
Interrupt enable bit
∗ IIEN4: UART Interrupt Enable Bit in the Interrupt Enable (ITC_EN) Register (D12/0x4302)
Interrupt level setting bit
∗ IILV4[2:0]: UART Interrupt Level Bits in the Internal Interrupt Level Setup (ITC_ILV2) Register 2
(D[2:0]/0x4312)
If an interrupt request pulse is output by the UART, the corresponding interrupt flag is set to 1.
If the interrupt enable bit corresponding to this interrupt flag is set to 1, the ITC sends an interrupt request to
the S1C17 core. To prohibit UART interrupts, set the interrupt enable bit to 0. The interrupt flag is set to 1 by a
UART interrupt request pulse, regardless of the interrupt enable bit setting (i.e., even if set to 0).
The interrupt level setting bit sets the UART interrupt level (0 to 7).
The S1C17 core accepts interrupts when all of the following conditions are met:
• The interrupt enable bit is set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit is set to 1.
• The UART interrupt has a higher interrupt level set than that set for the PSR IL (interrupt level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For detailed information on these interrupt registers and operations when interrupts occur, refer to "6 Interrupt
Controller (ITC)."
Interrupt vectors
The UART interrupt vector numbers and vector addresses are as listed below.
Vector number: 16 (0x10)
Vector address: 0x8040
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S1C17001 TECHNICAL MANUAL