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SP operation by the ret instruction
(1) [SP] → PC
(2) SP = SP + 4
SP
2.4.3 SP Operation when an Interrupt Occurs
If an interrupt or a software interrupt resulting from the int/intl instruction occurs, the processor enters an inter-
rupt handling process.
The processor saves the contents of the PC and PSR into the stack indicated by the SP before branching to the rel-
evant interrupt handler routine. This is to save the contents of the two registers before they are altered by interrupt
handling. The PC and PSR data is saved into the stack as shown in the diagram below.
For returning from the handler routine, the reti instruction is used to restore the contents of the PC and PSR from
the stack. In the reti instruction, the PC and PSR are read out of the stack, and the SP address is altered as shown
in the diagram below.
SP operation when an interrupt occurred
(1) SP = SP - 4
(2) PC + 2 → [SP]
(3) PSR → [SP + 3]
SP
SP operation when the reti instruction is executed
(1) [SP] → PC
(2) [SP+ 3] → PSR
(3) SP = SP + 4
SP
S1C17 CORE MANUAL
(Rev. 1.2)
0xffffff
7
0
SP = SP + 4
0x00
PC[23:16]
PC[15:8]
PC[7:0]
0x000000
Figure 2.4.2.2 SP and Stack (2)
0xffffff
7
0
SP = SP - 4
0x000000
Figure 2.4.3.1 SP and Stack (3)
0xffffff
7
0
SP = SP + 4
PSR
PC[23:16]
PC[15:8]
PC[7:0]
0x000000
Figure 2.4.3.2 SP and Stack (4)
Seiko Epson Corporation
2 REGISTERS
0xffffff
7
0
0x00
PC[23:16]
PC[15:8]
PC[7:0]
0x000000
0xffffff
7
0
0x00
PC[23:16]
PC[15:8]
PC[7:0]
0x000000
0xffffff
7
0
PSR
PC[23:16]
PC[15:8]
PC[7:0]
0x000000
2-5
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