Epson S1C17001 Technical Manual page 165

13 PWM & CAPTURE TIMER (T16E)
D3 CLKSEL: Input Clock Select Bit
Selects the timer input clock.
1 (R/W): External clock
0 (R/W): Internal clock (default)
If CLKSEL is written as 0, the internal clock (prescaler output) is selected as the timer input clock. If
written as 1, the external clock (clock input from EXCL3 (P27) pin) is selected and functions as an
event counter.
Note: To input the EXCL3 clock from the P27 port, P27MUX (D7/P2_PMUX register) must be
written as 1, and the P27 pin function must be changed beforehand.
∗ P27MUX: P27 Port Function Select Bit in the P2 Port Function Select (P2_PMUX) Register
D2 OUTEN: Clock Output Enable Bit
Controls the TOUT signal (timer output clock) output.
1 (R/W): Permitted
0 (R/W): Prohibited (default)
Writing 1 to OUTEN outputs the TOUT signal from the TOUT (P26) output pin. Writing 0 to OUTEN
halts output and switches to Off level in accordance with the INVOUT(D4) and INITOL(D8) settings.
P26 must be set to the TOUT pin using the P26 port function selection register before outputting the
TOUT signal.
D1 T16ERST: Timer Reset Bit
Resets the counter.
1 (W): Reset
0 (W): Disabled
0 (R): Normally 0 when read out (default)
Writing 1 to T16ERST resets the PWM & capture timer counter.
D0 T16ERUN: Timer Run/Stop Control Bit
Controls the timer Run/Stop.
1 (R/W): Run
0 (R/W): Stop (default)
The PWM & capture timer starts the count when T16ERUN is written as 1 and stops when written as 0.
The counter data is retained when stopped until the subsequent reset or run. Counting can be resumed
when switched from Stop to Run from the data retained.
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EPSON
S1C17001 TECHNICAL MANUAL