0X430E: Internal Interrupt Level Setup Register 0 (Itc_Ilv0) - Epson S1C17001 Technical Manual

0x430e: Internal Interrupt Level Setup Register 0 (ITC_ILV0)

Register name Address Bit
Internal Inter- 0x430e D15–11 –
rupt Level (16 bits)
D10–8 IILV1[2:0]
Setup Register 0
D7–3 –
(ITC_ILV0)
D2–0 IILV0[2:0]
D[15:11] Reserved
D[10:8] IILV1[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits
Set the 16-bit timer Ch.0 interrupt level (0 to 7). (Default: 0)
The S1C17 core does not accept interrupts with levels set lower than the PSR IL value.
The ITC uses the interrupt level when multiple interrupt factors occur simultaneously.
If multiple interrupts occur at the same time permi tted by the interrupt enable bit, the ITC sends the in-
terrupt request with the highest level set by the ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314)
to the S1C17 core.
If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the
lowest vector number is processed first. The other interrupts are held until all have been accepted by the
S1C17 core in descending order of priority.
If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the
S1C17 core (before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level
signal to the setting details of the most recent interrupt. The immediately preceding interrupt is held.
D[7:3] Reserved
D[2:0] IILV0[2:0]: 8-bit Timer Interrupt Level Bits
Set the 8-bit timer interrupt level (0 to 7). (Default: 0)
Refer to the IILV1[2:0] (D[10:8]) description.
S1C17001 TECHNICAL MANUAL
Name Function
reserved
T16 Ch.0 interrupt level
reserved
T8 interrupt level
EPSON
6 INITERRUPT CONTROLLER
Setting Init. R/W
– – – 0 when being read.
0 to 7 0x0 R/W
– – – 0 when being read.
0 to 7 0x0 R/W
Remarks
49