Epson S1C17001 Technical Manual page 248

PCLK
SPEN
SPI clock (Master mode)
SPTXD register
SPICLK pin
(CPOL = 0, CPHA = 1)
SPICLK pin
(CPOL = 0, CPHA = 0)
SDI pin
Shift register
SPI_RXD register
SPBSY
SPRBF
Interrupt
Blocking data transfers
After a data transfer is completed (both transmission and reception), data transfers are blocked by writing 0 to
the SPEN bit. Confirm that the SPTBE flag is 1 and the SPRBF flag is 0 before blocking data transfer.
Setting the SPEN bit to 0 empties the transmission and receive data buffers, clearing any remaining data. The
data being transferred cannot be guaranteed if SPEN is set to 0 while data is being sent or received.
S1C17001 TECHNICAL MANUAL
Write
Dummy
A A
D7 D6
Figure 19.5.2: Data transmit timing chart
EPSON
Write
Dummy
A B B
D0 D7 D6
Data A
Read
19 SPI
B
D0
Data B
239