Data Transfer Condition Settings - Epson S1C17001 Technical Manual

19 SPI

19.4 Data Transfer Condition Settings

The SPI module can be set to Master or Slave modes. The SPI clock polarity and phase can also be set via the
SPI_CTL register.
The data length is fixed at 8 bits.
Note: Make sure the SPI module is halted (when SPEN/SPI_CTL register = 0) before Master/Slave
mode selection and clock condition settings.
∗ SPEN: SPI Enable Bit in the SPI Control (SPI_CTL) Register (D0/0x4326)
Master/Slave mode selection
MSSL (D1/SPI_CTL register) is used to set the SPI module to Master mode or Slave mode. Setting MSSL to 1
sets Master mode; setting it to 0 (default) sets Slave mode. In Master mode, data is transferred using the inter-
nal clock. In Slave mode, data is transferred by inputting the master device clock.
∗ MSSL: Master/Slave Mode Select Bit in the SPI Control (SPI_CTL) Register (D1/0x4326)
SPI clock polarity and phase settings
The SPI clock polarity is selected by CPOL (D2/SPI_CTL register). Setting CPOL to 1 treats the SPI clock as
active Low; setting it to 0 (default) treats it as active High.
∗ CPOL: Clock Polarity Select Bit in the SPI Control (SPI_CTL) Register (D2/0x4326)
The SPI clock phase is selected by CPHA (D3/SPI_CTL register).
∗ CPHA: Clock Phase Select Bit in the SPI Control (SPI_CTL) Register (D3/0x4326)
As shown below, these control bits set transfer timing.
SPICLK(CPOL = 1, CPHA = 1)
SPICLK(CPOL = 1, CPHA = 0)
SPICLK(CPOL = 0, CPHA = 1)
SPICLK(CPOL = 0, CPHA = 0)
Receive data load timing
to shift register
236
SDI/SDO
D7 (MSB)
Figure 19.4.1: Clock and data transfer timing
EPSON
D0 (LSB)
S1C17001 TECHNICAL MANUAL