P0 Port Chattering Filter Function - Epson S1C17001 Technical Manual

10 INPUT/OUTPUT PORT (P)

10.6 P0 Port Chattering Filter Function

The P0 port includes a chattering filter circuit for key entry, which you can select to use or not use (and for which
you can select a verification time if used) individually for the four P0[3:0] and P0[7:4] ports using P0CFx[2:0]
(P0_CHAT register).
∗ P0CF1[2:0]: P0[3:0] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)
Register (D[2:0]/0x5208)
∗ P0CF2[2:0]: P0[7:4] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT)
Register (D[6:4]/0x5208)
Note: • The chattering filter verification time refers to the maximum pulse width that can be filtered.
Generating an input interrupt requires a minimum input time of the verification time and a
maximum input time of twice the verification time.
• Input interrupts will not be accepted for a transition into SLEEP mode with the chattering
filter left on. The chattering filter should be set off (no verification time) before executing the
slp command.
• P0 port interrupts must be blocked when P0_CHAT register (0x5208) settings are being
changed. Changing the setting while interrupts are permitted may generate inadvertent P0
interrupts.
• A phenomenon may occur in which the internal signal oscillates due to the time elapsed
until the signal reaches the threshold value if the input signal rise-up/drop-off time is de-
layed. Since input interrupts will malfunction under these conditions, the input signal rise-
up/drop-off time should normally be set to 25 ns or less.
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Table 10.6.1: Chattering filter function settings
P0CFx[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Default: 0x0, *when OSC3 = 2 MHz and PCLK = OSC3)
EPSON
Verification time *
16384/f (8ms)
PCLK
8192/f (4ms)
PCLK
4096/f (2ms)
PCLK
2048/f (1ms)
PCLK
1024/f (512μs)
PCLK
512/f (256μs)
PCLK
256/f (128μs)
PCLK
No verification time
(Off)
S1C17001 TECHNICAL MANUAL