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APPENDIX D INITIALIZATION ROUTINE
; ----- ITC (interrupt controller) ------
Xld.a
%r7, 0x4300
Xld.a
%r0, 0x1010
ext
0x06
ld
[%r7], %r0
Xld.a
%r0, 0x1010
ext
0x08
ld
[%r7], %r0
Xld.a
%r0, 0x0010
ext
0x0a
ld
[%r7], %r0
Xld.a
%r0, 0x1000
ext
0x0c
ld
[%r7], %r0
; ===== Main routine =========================================
...
; ======================================================================
;
Interrupt handler
; ======================================================================
; ----- Address unalign --------------------------
unalign_handler:
...
; ----- NMI -------------------------------------
nmi_handler:
...
(1) .rodata section is declared to position vector table in .vector section.
(2) Interrupt processing routine address is defined as vector.
IntXX_handler can be used as software interrupt.
(3) Program code is written in .text section.
(4) Sets stack pointer.
(5) Sets ROM read access cycles.
(See "3 Memory Map and Bus Control.")
(6) Sets interrupt trigger mode to level trigger for the following peripheral circuits.
P0 port, P1 port, stopwatch timer, clock timer, 8-bit OSC1 timer, PWM & capture timer
(See "6 Interrupt Controller (ITC).")
336
; ITC register base address
; P0, P1 interrupt level & trigger mode
; [0x4306] <= 0x1010
; SWT, CT interrupt level & trigger mode
; [0x4308] <= 0x1010
; T8OSC1 interrupt level & trigger mode
; [0x430a] <= 0x0010
; T16E interrupt level & trigger mode
; [0x430c] <= 0x1000
EPSON
. . . (6)
. . . (6)
. . . (6)
. . . (6)
S1C17001 TECHNICAL MANUAL
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