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11 16-bit Timer (T16)
11.1 16-bit Timer Overview
The S1C17001 incorporates a 3-channel 16-bit timer (T16).
The 16-bit timer consists of a 16-bit presettable down counter and a 16-bit reload data register holding the preset
values. The timer counts down from the initial value set in the reload data register and outputs an underflow signal
when the counter underflows. The underflow signal is used to generate an interrupt and an internal serial interface
clock. The underflow cycle can be programmed by selecting the prescaler clock and reload data, enabling the appli-
cation program to obtain time intervals and serial transfer speeds as required.
The timer also combines an event counter function via the input/output port pins and the external input signal pulse
width measurement function.
Figure 11.1.1 illustrates the 16-bit timer configuration.
P16 (Ch.0)
P07 (Ch.1)
P06 (Ch.2)
Prescaler
To ITC
To SPI (from Ch.1)
2
To I
C (from Ch.2)
Note: The 3-channel 16-bit timer module has the same functions except for the control register ad-
dress. The description in this section applies to all channels of the 16-bit timer. The "x" in the
register name refers to the channel number (0 to 2). The register addresses are referenced as
"Ch.0," "Ch.1," and "Ch.2."
Example: T16_CTLx register (0x4226/0x4246/0x4266)
Ch.0: T16_CTL0 register (0x4226)
Ch.1: T16_CTL1 register (0x4246)
Ch.2: T16_CTL2 register (0x4266)
S1C17001 TECHNICAL MANUAL
TRMD
Count mode selection
Operating mode
CKSL[1:0]
selection
External input signal
CKACTV
polarity selection
Count clock selection
DF[3:0]
-
PCLK
1/1 to 1/16 K
Interrupt request
Serial transfer clock
Figure 11.1.1: 16-bit timer configuration (1-channel)
EPSON
16-bit timer Ch.x
PRESER
Timer reset
PRUN
RUN/STOP control
Reload data register
Control
T16_TRx
circuit
Down counter
T16_TCx
11 16-BIT TIMER (T16)
Underflow
107
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