Clg Interrupt Flag Register - Epson S1C31W65 Technical Manual

Bits 5–4 OSC3INV[1:0]
These bits set the oscillation inverter gain when crystal/ceramic oscillator is selected as the OSC3 os-
cillator type.
Bit 3 Reserved
Bits 2–0 OSC3WT[2:0]
These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit.
Table 2.6.12 OSC3 Oscillation Stabilization Waiting Time Setting

CLG Interrupt Flag Register

Register name Bit
CLGINTF 15–9 –
8
7
6
5
4
3
2
1
0
Bits 15–9, 7, 6, 3 Reserved
Bit 8 IOSCTERIF
Bit 5 OSC1STPIF
Bit 4 IOSCTEDIF
Bit 2 OSC3STAIF
Bit 1 OSC1STAIF
Bit 0 IOSCSTAIF
These bits indicate the CLG interrupt cause occurrence statuses.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Table 2.6.11 OSC3 Oscillation Inverter Gain Setting
CLGOSC3.OSC3INV[1:0] bits
0x3
0x2
0x1
0x0
CLGOSC3.OSC3WT[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
IOSCTERIF
–
(reserved)
OSC1STPIF
IOSCTEDIF
–
OSC3STAIF
OSC1STAIF
IOSCSTAIF
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
1,024 clocks
256 clocks
64 clocks
16 clocks
4 clocks
Reset R/W
– R –
0 H0 R/W Cleared by writing 1.
0 – R –
0 H0 R
0 H0 R/W Cleared by writing 1.
0 H0 R/W
0 – R –
0 H0 R/W Cleared by writing 1.
0 H0 R/W
0 H0 R/W
Remarks
2-25