0X5205/5215: Px Port Interrupt Mask Registers (Px_Imsk) - Epson S1C17001 Technical Manual

0x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK)

Register name Address Bit
P0 Port 0x5205 D7–0 P0IE[7:0]
Interrupt Mask (8 bits)
Register
(P0_IMSK)
P1 Port 0x5215 D7–0 P1IE[7:0]
Interrupt Mask (8 bits)
Register
(P1_IMSK)
Note: The "x" in the bit names indicates the port number (0 or 1).
D[7:0] PxIE[7:0]: Px[7:0] Port Interrupt Enable Bits
Permit or prohibit P0[7:0] and P1[7:0] port interrupt.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
Setting PxIE[7:0] to 1 permits the corresponding interrupt, while setting to 0 blocks interrupts. Status
changes for the input pin with interrupt blocked do not affect interrupt occurrence.
To enable interrupt generation, the ITC P0 and P1 port interrupt enable bits must also be set to permit
interrupts.
S1C17001 TECHNICAL MANUAL
Name Function
P0[7:0] port interrupt enable
P1[7:0] port interrupt enable
EPSON
10 INPUT/OUTPUT PORT (P)
Setting Init. R/W
1 Enable 0 Disable
1 Enable 0 Disable
Remarks
0 R/W
0 R/W
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