Compare Data Settings - Epson S1C17001 Technical Manual

14.5 Compare Data Settings

Compare data is written to T8OCMP[7:0] (D[7:0]/T8OSC1_CMP register).
∗ T8OCMP[7:0]: Compare Data Bits in the 8-bit OSC1 Timer Compare Data (T8OSC1_CMP) Register (D[7:0]/0x50c2)
After initial resetting, the compare data register is set to 0x0.
The timer compares the count data against the compare data register and generates a compare match signal as well
as resets the counter if the values are equal. This compare match signal can generate an interrupt.
The compare match cycle can be calculated as follows:
Compare match interval = ————— [s]
Compare match cycle = ————— [Hz]
CMP: Compare data (T8OSC1_CMP register value)
clk_in: 8-bit OSC1 timer count clock frequency
S1C17001 TECHNICAL MANUAL
CMP + 1
clk_in
clk_in
CMP + 1
EPSON
14 8-BIT OSC1 TIMER (T8OSC1)
165