Pwm & Capture Timer Interrupts - Epson S1C17001 Technical Manual

13.7 PWM & Capture Timer Interrupts
The T16E module includes functions for generating the following two kinds of interrupts:
• Compare A match interrupt
• Compare B match interrupt
The T16E module outputs a single interrupt signal shared by the above two interrupt factors to the interrupt control-
ler (ITC). The interrupt flag within the T16E module should be read to identify the interrupt factor that occurred.
Compare A match interrupt
This interrupt request is generated when the counter matches the compare data A register setting during count-
ing. It sets the interrupt flag CAIF (D0/T16E_IFLG register) within the T16E module to 1.
∗ CAIF: Compare A Interrupt Flag in the PWM Timer Interrupt Flag (T16E_IFLG) Register (D0/0x530c)
To use this interrupt, set CAIE (D0/T16E_IMSK register) to 1. If CAIE is set to 0 (default), CAIF is not set to 1,
and the interrupt request for this factor is not sent to the ITC.
∗ CAIE: Compare A Interrupt Enable Bit in the PWM Timer Interrupt Mask (T16E_IMSK) Register (D0/0x530a)
If CAIF is set to 1, the T16E module outputs an interrupt request to the ITC. This interrupt request signal sets
the PWM & capture timer interrupt flag inside the ITC to 1 and generates an interrupt if the ITC and S1C17
core interrupt conditions are satisfied.
The CAIF should be read and checked in the PWM & capture timer interrupt processing routine to determine
whether the PWM & capture timer interrupt is due to compare A matching.
The interrupt factor should be cleared with the interrupt processing routine by resetting the T16E module CAIF
(to 1) rather than the ITC PWM & capture timer interrupt flag.
Compare B match interrupt
This interrupt request is generated when the counter matches the compare data B register setting during count-
ing. It sets the interrupt flag CBIF (D1/T16E_IFLG register) within the T16E module to 1.
∗ CBIF: Compare B Interrupt Flag in the PWM Timer Interrupt Flag (T16E_IFLG) Register (D1/0x530c)
To use this interrupt, set CBIE (D1/T16E_IMSK register) to 1. If CBIE is set to 0 (default), CBIF is not set to 1,
and the interrupt request for this factor is not sent to the ITC.
∗ CBIE: Compare B Interrupt Enable Bit in the PWM Timer Interrupt Mask (T16E_IMSK) Register (D1/0x530a)
If CBIF is set to 1, the T16E module outputs an interrupt request to the ITC. This interrupt request signal sets
the PWM & capture timer interrupt flag inside the ITC to 1 and generates an interrupt if the ITC and S1C17
core interrupt conditions are satisfied.
The CBIF should be read and checked in the PWM & capture timer interrupt processing routine to determine
whether the PWM & capture timer interrupt is due to compare B matching.
The interrupt factor should be cleared with the interrupt processing routine by resetting the T16E module CBIF (to
1) rather than the ITC PWM & capture timer interrupt flag.
Note: To prevent generating unnecessary interrupts, reset the corresponding CAIF or CBIF before
permitting compare A or compare B interrupts from CAIE or CBIE.
S1C17001 TECHNICAL MANUAL
13 PWM & CAPTURE TIMER (T16E)
EPSON
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