Epson S1C17001 Technical Manual page 157

13 PWM & CAPTURE TIMER (T16E)
Clock output Fine mode settings
With the default settings, the clock output changes at the input clock rise-up if the counter value matches the
compare data A.
If the counter data register T16ETC[14:0] matches the compare data A register T16ECA0[15:1], the Fine mode
clock output changes in accordance with the compare data A bit 0 (T16ECA0) value.
When T16ECA0 is 0: Changes at input clock rise-up.
When T16ECA0 is 1: Changes at half-cycle delayed input clock drop-off.
Input clock
Counter value
T16E_CA
T16E_CB
Compare A signal
Compare B signal
TOUT output (INVOUT = 0)
TOUT output (INVOUT = 1)
The output duty can thus be adjusted in Fine mode in input clock half-cycle steps. Note that a pulse will be out-
put with an input clock 1-cycle width when compare data A = 0 (same as for default). The maximum value for
compare data B in Fine mode is 2
B - 1).
Fine mode is set by SELFM (D6/T16E_CTL register).
∗ SELFM: Fine Mode Select Bit in the PWM Timer Control (T16E_CTL) Register (D6/0x5306)
Writing 1 to SELFM sets Fine mode. Fine mode is disabled after initial resetting.
Precautions
(1) Compare data should be set with A ≥ 0 and B ≥ 1 when using the timer output. The minimum settings are A
= 0 and B = 1, and the timer output cycle is half the input clock.
(2) Setting compare data with A > B (A > B x 2 for Fine mode) generates a compare B match signal only. It
does not generate a compare A match signal. In this case, the timer output is fixed at Low (High when IN-
VOUT = 1).
148
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3
2 3
Figure 13.6.3: Fine mode clock output
15 – 1 = 32,767, and the compare data A range will be 0 to (2 x compare data
EPSON
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