Epson S1C17001 Technical Manual page 247

19 SPI
PCLK
SPEN
SPI clock (Master mode)
SPTXD register
Shift register
SPICLK pin
(CPOL = 0, CPHA = 1)
SPICLK pin
(CPOL = 0, CPHA = 0)
SDO pin
SPBSY
SPTBE
Interrupt
Data receipt control
In Master mode, dummy data is written to the SPI_TXD register (0x4322). Writing to the SPI TXD register cre-
ates the trigger for receipt as well as transmission start. Writing actual transmission data enables simultaneous
transfers.
This starts the SPI clock output from SPICLK.
In Slave mode, the module waits until the clock is input from SPICLK. Slave mode involves only data receipt.
There is no need to write to the SPI_TXD register if no transmission is required. The receiving operation is
started by clock input from the master device. If data is transferred simultaneously, the transmission data is
written to the SPI_TXD register before the clock is input.
The data is loaded into the shift register in sequence with the MSB leading at the clock rising or tailing edge, as
determined by CPHA (D3/SPI_CTL register) and CPOL (D2/SPI_CTL register) (see Figure 19.4.1).
The received data is loaded into the receive data buffer once the 8 bits of data are received in the shift register.
Received data in the buffer can be read from the SPI_RXD register (0x4324)
∗ SPI_RXD: SPI Receive Data Register (0x4324)
The SPI module includes an SPRBF flag (D1/SPI_ST register) for receipt control.
∗ SPRBF: Receive Data Buffer Full Flag in the SPI Status (SPI_ST) Register (D1/0x4320)
The SPRBF flag indicates the receive data buffer status. This flag is set to 1 when the data received in the shift
register is loaded into the receive data buffer, indicating that the receive data can be read out. It reverts to 0
when the buffer data is read out from the SPI_RXD register. An interrupt can be generated as soon as the flag is
set to 1 (see Section 19.6). The received data should be read out either by using this interrupt or by inspecting
the SPRBF flag to confirm that the receive data buffer contains valid receive data. The receive data buffer is 1
byte in size, but a shift register is also provided, enabling received data to be retained in the buffer even while
the subsequent data is being received. Note that the receive data buffer should be read out before receiving the
subsequent data is complete. If receiving the subsequent data is complete before the receive data buffer contents
are read out, the newly received data will overwrite the previous received data in the buffer.
In Master mode, the SPBSY flag indicating the shift register state can be used in the same way while transfer-
ring data.
238
Write
Data A
A A
D7 D6
Transmit buffer empty
Figure 19.5.1: Data transmit timing chart
EPSON
Write
Data B
A B
D0 D7
S1C17001 TECHNICAL MANUAL