0X5346: Remc Interrupt Mask Register (Remc_Imsk) - Epson S1C17001 Technical Manual

0x5346: REMC Interrupt Mask Register (REMC_IMSK)

Register name Address Bit
REMC Interrupt 0x5346 D7–3 –
Mask Register (8 bits)
D2
(REMC_IMSK)
D1
D0
This register permits or blocks individual interrupt requests due to data length counter underflow, input signal rising
edge, or input signal falling edge. Setting the interrupt enable bit to 1 permits interrupt requests from corresponding
factors; setting it to 0 prevents interrupts. To generate interrupts, note that the ITC REMC interrupt enable bit must
also be set to permit interrupts.
D[7:3] Reserved
D2 REMFIE: Falling Edge Interrupt Enable Bit
Permits or blocks input signal falling edge interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
D1 REMRIE: Rising Edge Interrupt Enable Bit
Permits or blocks input signal rising edge interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
D0 REMUIE: Underflow Interrupt Enable Bit
Permits or blocks data length counter underflow interrupts.
1 (R/W): Interrupt permitted
0 (R/W): Interrupt prohibited (default)
S1C17001 TECHNICAL MANUAL
Name Function
reserved
REMFIE Falling edge interrupt enable
REMRIE Rising edge interrupt enable
REMUIE Underflow interrupt enable
EPSON
21 REMOTE CONTROLLER (REMC)
Setting Init. R/W
–
1 Enable 0 Disable
1 Enable 0 Disable
1 Enable 0 Disable
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
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