Epson S1C17001 Technical Manual page 314

Appendix A: I/O Register List
Peripheral circuit Address
Prescaler 0x4020
(8-bit device)
0x4021 to 0x403f –
UART (with IrDA) 0x4100
(8-bit device)
0x4101
0x4102
0x4103
0x4104
0x4105
0x4106 to 0x411f –
8-bit timer (with 0x4200
F mode) (16-bit
0x4202
device)
0x4204
0x4206
0x4208 to 0x421f –
16-bit timer Ch.0 0x4220
(16-bit device)
0x4222
0x4224
0x4226
0x4228 to 0x423f –
16-bit timer Ch.1 0x4240
(16-bit device)
0x4242
0x4244
0x4246
0x4248 to 0x425f –
16-bit timer Ch.2 0x4260
(16-bit device)
0x4262
0x4264
0x4266
0x4268 to 0x427f –
Interrupt controller 0x4300
(16-bit device)
0x4302
0x4304
0x4306
0x4308
0x430a
0x430c
0x430e
0x4310
0x4312
0x4314
0x4316 to 0x431f –
SPI 0x4320
(16-bit device)
0x4322
0x4324
0x4326
0x4328 to 0x433f –
2
I C 0x4340
(16-bit device)
0x4342
0x4344
0x4346
0x4348 to 0x435f –
S1C17001 TECHNICAL MANUAL
Register name
PSC_CTL Prescaler Control Register
–
UART_ST UART Status Register
UART_TXD UART Transmit Data Register
UART_RXD UART Receive Data Register
UART_MOD UART Mode Register
UART_CTL UART Control Register
UART_EXP UART Expansion Register
–
T8F_CLK 8-bit Timer Input Clock Select Register
T8F_TR 8-bit Timer Reload Data Register
T8F_TC 8-bit Timer Counter Data Register
T8F_CTL 8-bit Timer Control Register
–
T16_CLK0 16-bit Timer Ch.0 Input Clock Select Register
T16_TR0 16-bit Timer Ch.0 Reload Data Register
T16_TC0 16-bit Timer Ch.0 Counter Data Register
T16_CTL0 16-bit Timer Ch.0 Control Register
–
T16_CLK1 16-bit Timer Ch.1 Input Clock Select Register
T16_TR1 16-bit Timer Ch.1 Reload Data Register
T16_TC1 16-bit Timer Ch.1 Counter Data Register
T16_CTL1 16-bit Timer Ch.1 Control Register
–
T16_CLK2 16-bit Timer Ch.2 Input Clock Select Register
T16_TR2 16-bit Timer Ch.2 Reload Data Register
T16_TC2 16-bit Timer Ch.2 Counter Data Register
T16_CTL2 16-bit Timer Ch.2 Control Register
–
ITC_IFLG Interrupt Flag Register
ITC_EN Interrupt Enable Register
ITC_CTL ITC Control Register
ITC_ELV0 External Interrupt Level Setup Register 0
ITC_ELV1 External Interrupt Level Setup Register 1
ITC_ELV2 External Interrupt Level Setup Register 2
ITC_ELV3 External Interrupt Level Setup Register 3
ITC_ILV0 Internal Interrupt Level Setup Register 0
ITC_ILV1 Internal Interrupt Level Setup Register 1
ITC_ILV2 Internal Interrupt Level Setup Register 2
ITC_ILV3 Internal Interrupt Level Setup Register 3
–
SPI_ST SPI Status Register
SPI_TXD SPI Transmit Data Register
SPI_RXD SPI Receive Data Register
SPI_CTL SPI Control Register
–
2
I2C_EN I C Enable Register
2
I2C_CTL I C Control Register
I2C_DAT I 2 C Data Register
2
I2C_ICTL I C Interrupt Control Register
–
EPSON
APPENDIX A I/O REGISTER LIST
Function
Prescaler start/stop control
Reserved
Transfer, buffer, error status display
Transmission data
Receiving data
Transfer data format setting
Data transfer control
IrDA mode setting
Reserved
Prescaler output clock selection
Reload data setting
Counter data
Timer mode setting and timer RUN/STOP
Reserved
Prescaler output clock selection
Reload data setting
Counter data
Timer mode setting and timer RUN/STOP
Reserved
Prescaler output clock selection
Reload data setting
Counter data
Timer mode setting and timer RUN/STOP
Reserved
Prescaler output clock selection
Reload data setting
Counter data
Timer mode setting and timer RUN/STOP
Reserved
Interrupt occurrence status display/reset
Maskable interrupt permission/prevention
ITC operation permission/prevention
P0/P1 port interrupt level and trigger mode
setting
Stopwatch timer and clock timer interrupt
level and trigger mode setting
8-bit OSC1 timer interrupt level and trigger
mode setting
PWM & capture timer interrupt level and
trigger mode setting
8-bit timer and 16-bit timer Ch.0 interrupt
level setting
16-bit timer Ch.1 and 16-bit timer Ch.2
interrupt level setting
UART and remote controller interrupt level
setting
2
SPI and I C interrupt level setting
Reserved
Transfer and buffer status display
Transmission data
Receiving data
SPI mode and data transfer permission
setting
Reserved
2
I C module enable
2
I C control and transfer status display
Transfer data
2
I C interrupt control
Reserved
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