0X4306: External Interrupt Level Setup Register 0 (Itc_Elv0) - Epson S1C17001 Technical Manual

0x4306: External Interrupt Level Setup Register 0 (ITC_ELV0)

Register name Address Bit
External 0x4306 D15–13 –
Interrupt Level (16 bits)
D12
Setup Register 0
D11
(ITC_ELV0)
D10–8 EILV1[2:0]
D7–5 –
D4
D3
D2–0 EILV0[2:0]
D[15:13] Reserved
D12 EITG1: P1 Port Interrupt Trigger Mode Select Bit
Selects P1 port interrupt trigger mode. This should be set to 1 for the S1C17001.
1 (R/W): Level trigger mode
0 (R/W): Pulse trigger mode (default)
In pulse trigger mode, the ITC samples interrupt signals using system clock rising edges. When the
pulse High period is detected, the ITC sets the interrupt flag (EIFTx) to 1 and stops sampling that inter-
rupt signal. The ITC resumes interrupt signal sampling after the application program (interrupt process-
ing routine) resets the interrupt flag (EIFTx) to 0.
In level trigger mode, the ITC samples interrupt signals using system clock rising edges. When High
level is detected, the interrupt flag (EIFTx) is set to 1 and is subsequently reset to 0 when Low level is
detected. Interrupt flags (EIFTx) cannot be reset by writing 1 in this mode. The interrupt signal must be
maintained at High until the interrupt source module is accepted by the S1C17 core, and the interrupt
signal must then be cleared.
D11 Reserved
D[10:8] EILV1[2:0]: P1 Port Interrupt Level Bits
Set the P1 port interrupt level (0 to 7). (Default: 0)
The S1C17 core does not accept interrupts with levels set lower than the PSR IL value.
The ITC uses the interrupt level when multiple interrupt factors occur simultaneously.
If multiple interrupts occur at the same time permitted by the interrupt enable bit, the ITC sends the in-
terrupt request with the highest level set by the ITC_ELVx and ITC_ILVx registers (0x4306 to 0x4314)
to the S1C17 core.
If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the
lowest vector number is processed first. The other interrupts are held until all have been accepted by the
S1C17 core in descending order of priority.
If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the
S1C17 core (before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level
signal to the setting details of the most recent interrupt. The immediately preceding interrupt is held.
D[7:5] Reserved
D4 EITG0: P0 Port Interrupt Trigger Mode Select Bit
Selects P0 port interrupt trigger mode. This should be set to 1 for the S1C17001.
1 (R/W): Level trigger mode
0 (R/W): Pulse trigger mode (default)
Refer to the EITG1 (D12) description.
D3 Reserved
D[2:0] EILV0[2:0]: P0 Port Interrupt Level Bits
Set the P0 port interrupt level (0 to 7). (Default: 0)
Refer to the EILV1[2:0] (D[10:8]) description.
S1C17001 TECHNICAL MANUAL
Name Function
reserved
EITG1 P1 interrupt trigger mode
– reserved
P1 interrupt level
reserved
EITG0 P0 interrupt trigger mode
– reserved
P0 interrupt level
EPSON
6 INITERRUPT CONTROLLER
Setting Init. R/W
–
1 Level 0 Pulse
–
0 to 7 0x0 R/W
–
1 Level 0 Pulse
–
0 to 7 0x0 R/W
Remarks
– – 0 when being read.
0 R/W Be sure to set to 1.
– – 0 when being read.
– – 0 when being read.
0 R/W Be sure to set to 1.
– – 0 when being read.
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