0X5000: Clock Timer Control Register (Ct_Ctl) - Epson S1C17001 Technical Manual

15 CLOCK TIMER (TC)

0x5000: Clock Timer Control Register (CT_CTL)

Register name Address Bit
Clock Timer 0x5000 D7–5 –
Control Register (8 bits)
D4
(CT_CTL) D3–1 –
D0
D[7:5] Reserved
D4 CTRST: Clock Timer Reset Bit
Resets the clock timer.
1 (W): Reset
0 (W): Disabled
0 (R): Normally 0 when read out (default)
Writing 1 to this bit resets the counter to 0x0. When reset in Run state, the clock timer restarts immedi-
ately after resetting. The reset data 0x0 is retained when in Stop state.
D[3:1] Reserved
D0 CTRUN: Clock Timer Run/Stop Control Bit
Controls the clock timer Run/Stop.
1 (R/W): Run
0 (R/W): Stop (default)
The clock timer starts counting when CTRUN is written as 1 and stops when written as 0. The counter
data is retained at Stop state until a reset or the next Run state.
184
Name Function
reserved
CTRST Clock timer reset
reserved
CTRUN Clock timer run/stop control
Setting
–
1 Reset 0 Ignored
–
1 Run 0 Stop
EPSON
Init. R/W Remarks
– – 0 when being read.
0 W
– –
0 R/W
S1C17001 TECHNICAL MANUAL