Table of Contents
Advertisement
2
0x4342: I
C Control Register (I2C_CTL)
Register name Address
Bit
I
2
C Control
0x4342
D15–10 –
Register
(16 bits)
D9
(I2C_CTL)
D8
D7–5 –
D4
D3–2 –
D1
D0
D[15:10] Reserved
D9
RBUSY: Receive Busy Flag
Indicates the I
1 (R):
Operating
0 (R):
Standby (default)
RBUSY is set to 1 when the I
way. It is cleared to 0 once receipt is complete or in Wait state.
D8
TBUSY: Transmit Busy Flag
Indicates the I
1 (R):
Operating
0 (R):
Standby (default)
TBUSY is set to 1 when the I
underway. It is cleared to 0 once transmission is complete. It is also returned to 0 in Wait state.
D[7:5]
Reserved
D4
NSERM: Noise Remove On/Off Bit
Turns the noise filter function on or off.
1 (R/W): On
0 (R/W): Off (default)
The I
C module incorporates a function for filtering noise from the SDA and SCL pin input signals.
2
This function is enabled by setting NSERM to 1.
Note that using this function requires setting the I
1/6 or less of PCLK.
D[3:2]
Reserved
D1
STP: Stop Control Bit
Generates the stop condition.
1 (R/W): Stop condition generated
0 (R/W): Disabled (default)
With STP set at 1, the I
High while maintaining the I
Note that the stop condition will be generated only if STP is 1 and TXE (D9/I2C_DAT register), RXE
(D10/I2C_DAT register), and STRT (D0) are set to 0 when data transfer is complete (including ACK
transfer). STP is disabled if any of TXE, RXE, or STRT is 1.
STP is automatically reset to 0 if the stop condition is generated.
S1C17001 TECHNICAL MANUAL
Name
Function
reserved
RBUSY
Receive busy flag
TBUSY
Transmit busy flag
reserved
NSERM
Noise remove on/off
reserved
STP
Stop control
STRT
Start control
2
C receipt status.
2
C starts data receiving and is maintained at 1 while receiving is under-
2
C transmission status.
C starts data transmission and is maintained at 1 while transmission is
2
C module generates the stop condition by changing the SDA line from Low to
2
2
C bus SCL line at High. The I
Setting
–
1 Busy
0 Idle
1 Busy
0 Idle
–
1 On
0 Off
–
1 Stop
0 Ignored
1 Start
0 Ignored
C clock (16-bit timer Ch.2 output clock) frequency to
2
2
C bus subsequently becomes free.
EPSON
2
20 I
C
Init. R/W
Remarks
–
–
0 when being read.
0
R
0
R
–
–
0 when being read.
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
263
Advertisement
Table of Contents
